S9S08SG16E1CTJ Freescale, S9S08SG16E1CTJ Datasheet - Page 286

• Manufacturer Part Number: S9S08SG16E1CTJ
• Manufacturer: Freescale

Specifications of S9S08SG16E1CTJ

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 1KB
• # I/os (max): 16
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Package Type: TSSOP
• Program Memory Type: Flash
• Program Memory Size: 16KB
• Lead Free Status / RoHS Status: Compliant

Chapter 17 Development Support
1
17.4.3
The debug module includes nine bytes of register space for three 16-bit registers and three 8-bit control
and status registers. These registers are located in the high register space of the normal memory map so
they are accessible to normal application programs. These registers are rarely if ever accessed by normal
user application programs with the possible exception of a ROM patching mechanism that uses the
breakpoint logic.
17.4.3.1
This register contains compare value bits for the high-order eight bits of comparator A. This register is
forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.
17.4.3.2
This register contains compare value bits for the low-order eight bits of comparator A. This register is
forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.
17.4.3.3
This register contains compare value bits for the high-order eight bits of comparator B. This register is
forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.
17.4.3.4
This register contains compare value bits for the low-order eight bits of comparator B. This register is
forced to 0x00 at reset and can be read at any time or written at any time unless ARM = 1.
286
Reset
BDFR is writable only through serial background mode debug commands, not from user programs.
BDFR
Field
W
0
R
DBG Registers and Control Bits
Background Debug Force Reset — A serial active background mode command such as WRITE_BYTE allows
an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot
be written from a user program.
0
0
7
Debug Comparator A High Register (DBGCAH)
Debug Comparator A Low Register (DBGCAL)
Debug Comparator B High Register (DBGCBH)
Debug Comparator B Low Register (DBGCBL)
Figure 17-6. System Background Debug Force Reset Register (SBDFR)
= Unimplemented or Reserved
0
0
6
Table 17-3. SBDFR Register Field Description
0
0
5
MC9S08SG32 Data Sheet, Rev. 8
0
0
4
Description
0
0
3
0
0
2
Freescale Semiconductor
1
0
0
BDFR
0
0
0
1