S9S08SG16E1CTJ Freescale, S9S08SG16E1CTJ Datasheet - Page 17

• Manufacturer Part Number: S9S08SG16E1CTJ
• Manufacturer: Freescale

Specifications of S9S08SG16E1CTJ

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 1KB
• # I/os (max): 16
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Package Type: TSSOP
• Program Memory Type: Flash
• Program Memory Size: 16KB
• Lead Free Status / RoHS Status: Compliant

Section Number
13.5 Initialization/Application Information .......................................................................................... 202
14.1 Introduction ................................................................................................................................... 205
14.2 Register Definition ........................................................................................................................ 210
14.3 Functional Description .................................................................................................................. 217
15.1 Introduction ................................................................................................................................... 225
15.2 External Signal Description .......................................................................................................... 230
15.3 Modes of Operation....................................................................................................................... 231
15.4 Register Definition ........................................................................................................................ 231
Freescale Semiconductor
14.1.1 Features ........................................................................................................................... 207
14.1.2 Modes of Operation ........................................................................................................ 207
14.1.3 Block Diagram ................................................................................................................ 208
14.2.1 SCI Baud Rate Registers (SCIBDH, SCIBDL) .............................................................. 210
14.2.2 SCI Control Register 1 (SCIC1) ..................................................................................... 211
14.2.3 SCI Control Register 2 (SCIC2) ..................................................................................... 212
14.2.4 SCI Status Register 1 (SCIS1) ........................................................................................ 213
14.2.5 SCI Status Register 2 (SCIS2) ........................................................................................ 215
14.2.6 SCI Control Register 3 (SCIC3) ..................................................................................... 216
14.2.7 SCI Data Register (SCID)............................................................................................... 217
14.3.1 Baud Rate Generation ..................................................................................................... 217
14.3.2 Transmitter Functional Description ................................................................................ 218
14.3.3 Receiver Functional Description..................................................................................... 219
14.3.4 Interrupts and Status Flags.............................................................................................. 221
14.3.5 Additional SCI Functions ............................................................................................... 222
15.1.1 Features ........................................................................................................................... 227
15.1.2 Block Diagrams .............................................................................................................. 227
15.1.3 SPI Baud Rate Generation .............................................................................................. 229
15.2.1 SPSCK — SPI Serial Clock............................................................................................ 230
15.2.2 MOSI — Master Data Out, Slave Data In ...................................................................... 230
15.2.3 MISO — Master Data In, Slave Data Out ...................................................................... 230
15.2.4 SS — Slave Select........................................................................................................... 230
15.3.1 SPI in Stop Modes .......................................................................................................... 231
15.4.1 SPI Control Register 1 (SPIC1) ...................................................................................... 231
15.4.2 SPI Control Register 2 (SPIC2) ...................................................................................... 232
15.4.3 SPI Baud Rate Register (SPIBR).................................................................................... 233
15.4.4 SPI Status Register (SPIS) .............................................................................................. 234
15.4.5 SPI Data Register (SPID)................................................................................................ 235
Serial Communications Interface (S08SCIV4)
Serial Peripheral Interface (S08SPIV3)
MC9S08SG32 Data Sheet, Rev. 8
Chapter 14
Chapter 15
Title
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