MCIMX515DJM8C Freescale, MCIMX515DJM8C Datasheet

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MCIMX515DJM8C

Manufacturer Part Number
MCIMX515DJM8C
Description
Manufacturer
Freescale
Datasheet

Specifications of MCIMX515DJM8C

Operating Temperature (min)
-20C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant

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Freescale Semiconductor
Data Sheet: Technical Data
i.MX51 Applications
Processors for Consumer and
Industrial Products
1
The i.MX51 multimedia applications processors
represent Freescale Semiconductor’s latest addition to a
growing family of multimedia-focused products offering
high performance processing optimized for lowest
power consumption.
The i.MX51 processors feature Freescale’s advanced and
power-efficient implementation of the ARM Cortex
A8™ core, which operates at speeds as high as
800 MHz. Up to 200 MHz DDR2 and mobile DDR
DRAM clock rates are supported. These devices are
suitable for applications such as the following:
© Freescale Semiconductor, Inc., 2009-2010. All rights reserved.
Introduction
Netbooks (web tablets)
Nettops (internet desktop devices)
Mobile internet devices (MID)
Portable media players (PMP)
Portable navigation devices (PND)
High-end PDAs
Gaming consoles
Automotive navigation and entertainment (see
automotive data sheet, IMX51AEC)
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3. IOMUX Configuration for Boot Media . . . . . . . . . . . . . . 14
4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 17
5. Package Information and Contact Assignments . . . . . 150
6. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
1.1.
1.2.
2.1.
3.1.
3.2.
3.3.
3.4.
3.5.
3.6.
3.7.
4.1.
4.2.
4.3.
4.4.
4.5.
4.6.
4.7.
5.1.
5.2.
5.3.
5.4.
See
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Special Signal Considerations . . . . . . . . . . . . . . . 12
NAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
SD/MMC IOMUX Pin Configuration . . . . . . . . . . . 15
I
eCSPI/CSPI IOMUX Pin Configuration . . . . . . . . 16
Wireless External Interface Module (WEIM) . . . . 16
UART IOMUX Pin Configuration . . . . . . . . . . . . . 16
USB-OTG IOMUX Pin Configuration . . . . . . . . . . 16
Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . 17
Supply Power-Up/Power-Down Requirements and
Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 24
Output Buffer Impedance Characteristics . . . . . . 31
I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 34
Module Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
External Peripheral Interfaces . . . . . . . . . . . . . . . 70
13 x 13 mm Package Information . . . . . . . . . . . . 150
19 x 19 mm Package Information . . . . . . . . . . . . 169
13 × 13 mm, 0.5 Pitch Ball Map . . . . . . . . . . . . . 187
19 x 19 mm, 0.8 Pitch Ball Map . . . . . . . . . . . . . 192
Table 1
2
Case 2058 13 x 13 mm, 0.5 mm pitch
Case 2017 19 x 19 mm, 0.8 mm pitch
C IOMUX Pin Configuration . . . . . . . . . . . . . . . . 15
Document Number: IMX51CEC
Package Information
Ordering Information
on page 3 for ordering information.
Plastic Package
IMX51
Rev. 4, 08/2010

Related parts for MCIMX515DJM8C

MCIMX515DJM8C Summary of contents

Page 1

... High-end PDAs • Gaming consoles • Automotive navigation and entertainment (see automotive data sheet, IMX51AEC) © Freescale Semiconductor, Inc., 2009-2010. All rights reserved. Document Number: IMX51CEC Rev. 4, 08/2010 IMX51 Package Information Plastic Package Case 2058 mm, 0.5 mm pitch Case 2017 mm, 0.8 mm pitch ...

Page 2

... Applications Processor—The i.MX51 processors boost the capabilities of high-tier portable applications by providing for the ever-increasing MIPS needs of operating systems and games. Freescale’s Dynamic Voltage and Frequency Scaling (DVFS) allows the device run at much lower voltage and frequency with sufficient MIPS for tasks such as audio decode resulting in significant power reduction. • ...

Page 3

... No hardware graphics accelerators MCIMX513CJM6C M77X No hardware graphics accelerators MCIMX513DJM8C M77X No hardware graphics accelerators MCIMX515CJM6C M77X Full specification MCIMX515DJM8C M77X Full specification MCIMX515DVK8C! M77X Full specification 1 For Junction Temperature (Tj) maximum ratings, refer to 2 Case 2017 and Case 2058 are RoHS compliant, lead-free, MSL = 3. ...

Page 4

... ETM, CTI0,1 GPIOx32 (4) SJC SSI (3) Video Proc. Unit FIRI (VPU) Debug 3D Graphics DAP Proc Unit (GPU) TPIU CTI (2) Clock and Reset Graphics PLL (3) Memory (128 Kbytes) CCM GPC 2D Graphics SRC Proc Unit XTALOSC (GPU2D) CAMP (2) Access. Keypad MMC/SDIO Conn. Freescale Semiconductor ...

Page 5

... System System Control i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Table 2. i.MX51 Digital and Analog Modules 1-Wire support provided for interfacing with an on-board EEPROM, and smart battery interfaces, for example: Dallas DS2502. The ARM Cortex A8™ Core Platform consists of the ARM Cortex A8™ ...

Page 6

... Full-/high-speed mode • Host clock frequency variable between 32 kHz to 52 MHz • 200 Mbps data transfer for SD/SDIO cards using four parallel data lines • 416 Mbps data transfer for MMC cards using eight parallel data lines Freescale Semiconductor ...

Page 7

... Peripherals 2 HS-I C i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Brief Description Can be configured as eSDHC (see above) and is muxed with the P-ATA interface. The Ethernet Media Access Controller (MAC) is designed to support both 10 Mbps and 100 Mbps ethernet/IEEE Std 802.3™ networks. An external transceiver interface and transceiver function are required to complete the interface to the media ...

Page 8

... The pulse-width modulator (PWM) has a 16-bit counter and is optimized to generate sound from stored sample audio images. It can also generate tones. The PWM uses 16-bit resolution and data FIFO to generate sound. Unified RAM, can be split between Secure RAM and Non-Secure RAM Supports secure and regular Boot Modes Freescale Semiconductor ...

Page 9

... Peripherals Module Interface i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Brief Description Protecting read-only data from modification is one of the basic elements in trusted platforms. The Run-Time Integrity Checker v3 (RTICv3) module data monitoring device responsible for ensuring that memory content is not corrupted during program execution ...

Page 10

... S-video, and component video up to HD720p/1080i. The TrustZone Interrupt Controller (TZIC) collects interrupt requests from all i.MX51 sources and routes them to the ARM core. Each interrupt can be configured as a normal or a secure interrupt. Software Force Registers and software Priority Masking are also supported. Freescale Semiconductor ...

Page 11

... Programmable baud rates MHz. This is a higher max baud rate relative to the 1.875 MHz, which is stated by the TIA/EIA-232-F standard and previous Freescale UART modules. • 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting auto-baud • IrDA 1.0 support (up to SIR speed of 115200 bps) • ...

Page 12

... EXTAL/XTAL. To use a reference in the kilohertz range per Table 59, tie CLK_SS to NVCC_PER3 to select CKIL. After initialization, the reference clock source can be changed (initial setting is overwritten). Note: Because this input has a keeper circuit, Freescale recommends tying this input to directly to GND or NVCC_PER3 series resistor is used its value must be COMP The user should bypass this reference with an external 0 ...

Page 13

... STR This signal is reserved for Freescale manufacturing use. The user should float this signal. TEST_MODE TEST_MODE is for Freescale factory use only. This signal is internally connected to an on-chip pull-down device. Users must either float this signal or tie it to GND. VREF When using VREF with DDR-2 I/O, the nominal 0.9 V reference voltage must be half of the NVCC_EMI_DRAM supply. The user must tie VREF to a precision external resistor divider. Use a 1 kΩ ...

Page 14

... The user should tie a fundamental-mode crystal across XTAL and EXTAL. The crystal must be rated for a maximum drive level of 100 80 Ω or less is recommended. Freescale BSP (Board Support Package) software requires 24 MHz on EXTAL. The crystal can be eliminated if an external 24 MHz oscillator is available. In this case, EXTAL must be directly driven by the external oscillator and XTAL is floated ...

Page 15

... I C IOMUX Pin Configuration The contacts assigned to the signals used by the three I Signal HSI SDA I2C1_DAT.alt0 SCL I2C1_CLK.alt0 i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Table 5. SD/MMC IOMUX Pin Configuration eSDHC2 SD2_CLK.alt0 SD2_CMD.alt0 SD2_DATA0.alt0 1 N/A N/A SD2_DATA3.alt0 ...

Page 16

... Table 8. UART IOMUX Pin Configuration UART1 UART1_TXD.alt0 UART2_TXD.alt0 UART1_RXD.alt0 UART2_RXD.alt0 UART1_CTS.alt0 USBH1_DATA0.alt1 UART1_RTS.alt0 USBH1_DATA3.alt1 Table 9. ULPI PHY IOMUX Pin Configuration Table 7. CSPI USBH1_NXT.alt1 USBH1_DIR.alt1 USBH1_STP.alt1 USBH1_CLK.alt1 N/A USBH1_DATA5.alt1 N/A N/A Table 8. UART2 UART3 UART3_TXD.alt1 UART3_RXD.alt1 KEY_COL5.alt2 KEY_COL4.alt2 ULPI PHY GPIO1_8.alt1 GPIO1_9.alt1 Freescale Semiconductor ...

Page 17

... Table 13 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Table 10. i.MX51 Chip-Level Conditions Data” CAUTION Table 11 ...

Page 18

... Table 12. Thermal Resistance Data Board — — Min Max Unit –0.3 1.35 V –0.3 1.15 V –0.5 3.6 V –0.5 3.3 V — 5. –0.5 OVDD + 0 — 2000 — 500 o –40 125 o — 105 o — 105 Symbol Value Unit R 6 °C/W θ °C/W θJC is measured case Freescale Semiconductor ...

Page 19

... Memory arrays voltage—Run Mode Memory arrays voltage—Stop Mode VDD_DIG_PLL_A PLL Digital supplies VDD_DIG_PLL_B VDD_ANA_PLL_A PLL Analog supplies VDD_ANA_PLL_B i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Table 13. i.MX51 Operating Ranges Parameter ≤ 167 MHz ≤ 800 MHz ≤ 600 MHz ...

Page 20

... Freescale Semiconductor Unit — ...

Page 21

... In Read mode, Freescale recommends VDD_FUSE be floated or grounded. Tying VDD_FUSE to a positive supply (3.0 V–3.3 V) increases the possibility of inadvertently blowing fuses and is not recommended. 5 The NAND Flash supplies are composed of three groups and C. Each group can be powered with a different supply voltage. For example, NVCC_NANDF_A = 1.8 V, NVCC_NANDF_B = 3.0 V, NVCC_NANDF_C = 2.7 V. ...

Page 22

... Applications Processors for Consumer and Industrial Products, Rev Condition = 25° ° °C A Supply Nominal Unit VDDGP 0.24 mA VCC 0.45 VDDA 0.2 NVCC_OSC 0.012 Total 1.09 mW VDDGP 0.24 mA VCC 0.45 VDDA 0.2 NVCC_OSC 1.5 Total 4.8 mW VDDGP 50 mA VCC 2 VDDA 1.15 NVCC_OSC 1.5 Total 63 mW Freescale Semiconductor ...

Page 23

... Excessive current during power-up phase • Prevention of the device from booting • Irreversible damage to the i.MX51 processor (worst-case scenario) i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Table 17. USB PHY Current Consumption Conditions RX Full Speed TX RX High Speed ...

Page 24

... C and I C • Enhanced Secure Digital Host Controller (eSDHC) i.MX51 Applications Processors for Consumer and Industrial Products, Rev NVCC_HS4_1 NVCC_HS4_2 NVCC_HS6 NVCC_HS10 VDD_DIG_PLL_A/B 2 VDD_ANA_PLL_A/B NVCC_PERx NVCC_EMI NVCC_IPU NVCC_I2C Figure 2. Power-Up Sequence NOTE AHVDDRGB VDD_FUSE NVCC_TV_BACK TVDAC_DHVDD NVCC_OSC NVCC_USBPHY VDDA33 Freescale Semiconductor 1 ...

Page 25

... DC level, VIL or VIH. Monotonic input transition time is from 0 Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled. 3 I/O leakage currents are listed in Table i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor NOTE Table 128 Symbol Test Conditions Voh Iout = -1 mA ...

Page 26

... Min Typ Max OVDD – 0.15 — — — — 0.15 — — –2.1 –4.2 –6.3 –8.4 — — 2.1 4.2 6.3 8.4 0.7 × OVDD — OVDD 0.3 × OVDD 0 — 0.35 0.62 — 1.27 Freescale Semiconductor Unit — Unit ...

Page 27

... High-level output current, high voltage mode Low-level output current, low voltage mode Low-level output current, high voltage mode 1 2 High-Level DC input voltage , 2,3 Low-Level DC input voltage i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Symbol Test Conditions VT+ — VT– — Iin OVDD Iin ...

Page 28

... Table 13, unless Typ Max Unit — 0.4 V — OVDD V 0.3 × OVDD — V — — V — — V 0.5 × OVDD — — See Note — Freescale Semiconductor ...

Page 29

... VOH Output Low Voltage VOL Table 24. USB Interface Electrical Specification Parameter Symbol Input High Voltage VIH Input Low Voltage VIL i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor 25. Signals Min USB_VPOUT VDD x 0.7 USB_VMOUT USB_XRXD, USB_VPIN, USB_VMIN USB_VPOUT ...

Page 30

... Freescale Semiconductor ...

Page 31

... Low Drive Strength, Ztl = 150 Ω Output Driver Rpd Medium Drive Strength, Ztl = 75 Ω Impedance High Drive Strength, Ztl = 50 Ω Max Drive Strength i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Table 26. LVIO I/O Output Buffer Impedance Conditions Min OVDD 2.775 V OVDD 1.875 ...

Page 32

... Applications Processors for Consumer and Industrial Products, Rev Table 28. UHVIO Output Buffer Impedance Min OVDD OVDD 1. 114 118 49 32 NOTE Typ Max OVDD OVDD OVDD OVDD 1.875 V 3.3 V 1.65 V 3.6 V 124 135 198 206 103 126 154 179 217 109 Figure 3). Freescale Semiconductor Unit Ω 69 Ω 72 ...

Page 33

... Vref1 Vref 0 Vovdd – Vref1 Rpu = Rpd = Vovdd – Vref2 Figure 3. Impedance Matching Load for Measurement i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor OVDD PMOS (Rpu) Ztl Ω inches pad NMOS (Rpd) OVSS Vref2 × Ztl Vref1 Vref2 × ...

Page 34

... Freescale Semiconductor Unit V/ns V/ns V/ns V/ns mA/ns mA/ns mA/ns ...

Page 35

... Hysteresis mode is recommended for inputs with transition time greater than 25 ns. 2 4.5 Parameters See the errata for HS-I 2 standard I C modules have no errata i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Symbol Test Condition Min Rise/Fall tdit — trm — Table 30. Fast I/O AC Parameters Test Symbol Min Rise/Fall ...

Page 36

... CL includes package, probe, and fixture capacitance. 70% 30% t TLH PA3Max = max of t TLH PA4Max = max t THL Figure 9. Definition of Timing for HS-Mode Figure 7 depicts the output Figure 9 depicts HS-mode timing OVDD 70% 30 × × OVDD and 0.7 OVDD OVDD 70% 30 THL and t THL Freescale Semiconductor Figure 8 ...

Page 37

... Output fall time at SDAH (low driver strength) Output fall time at SDAH (medium driver strength) i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor 2 C I/O are listed in the tables from the Table 2 C Standard- and Fast-Mode Electrical Parameters ...

Page 38

... Typ Max Rise/Fall — — 3/3 6/5 — — 5/5 9/9 0/0 — — 0/0 0/0 — — 0/0 — — 36 — — 16 — — 25 Freescale Semiconductor Unit Unit mA/ns mA/ns ns Unit ns ns V/ns V/ns mA/ns mA/ns ns ...

Page 39

... Table 37. AC Electrical Characteristics of DDR2 IO Pads for Fast mode and Parameter 1 Output Pad Transition Times Output Pad Propagation Delay, 50%-50% 1 Output Pad Slew Rate i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor for ovdd=1.65 – 1.95 V (ipp_hve=0) Test Symbol Condition rise/fall tpr 15pF ...

Page 40

... Min Max Typ rise/fall 0.70/0.74 1.06/1.00 1.18/1.21 1.49/1.47 1.90/1.95 3.23/3.10 2.36/2.48 3.82/3.75 1.54/1.46 0.93/0.99 0.92/0.89 0.66/0. mA/ns 0.6/0.58 0.9/0.88 0.71/0.7 1.03/0.98 0.58/0.61 1.014/1.07 — — 5 Freescale Semiconductor Units Units ...

Page 41

... Input Pad Propagation Delay with Hysteresis 2 (CMOS input), 50%-50% Input Pad Propagation Delay (DDR input), 2 50%-50% 3 Maximum Input Transition Times i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor ovdd=1.65 – 1.95 V (ipp_hve=0) Test Symbol Condition 1 tpr 15pF 35pF ...

Page 42

... Freescale Semiconductor Units V/ns V/ns V/ns mA/ns mA/ns mA/ — ns ...

Page 43

... Table 42. AC Electrical Characteristics of DDR2_clk IO Pads for Slow mode and for Parameter 1 Output Pad Transition Times Output Pad Propagation Delay, 50%-50% 1 Output Pad Slew Rate i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor for ovdd=1.65 – 1.95 V Test Min Symbol Condition rise/fall tpr 15pF 0 ...

Page 44

... Freescale Semiconductor Units mA/ Units V/ns V/ns V/ns mA/ns mA/ns ...

Page 45

... Output Pad Slew Rate (High Drive) Output Pad Slew Rate (Medium Drive) Output Pad Slew Rate (Low Drive) 1 Output Pad di/dt (High Drive) 1 Output Pad di/dt (Medium drive) i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Test Symbol Condition di/dt — trfi 1.2 pF tpi 1 ...

Page 46

... Table 45 lists the timing parameters. CC1 Figure 12. Reset Timing Diagram Table 45. Reset Timing Parameters Parameter Min Max Typ rise/fall rise/fall 0.09/0.09 0.132/0.128 0.212/0.213 0.3/0.36 0.5/0.52 0.82/0.94 — — 5 Min Max 50 — Freescale Semiconductor Units mA/ns ns — ns Unit ns ...

Page 47

... Input frequency VIL (for square wave input) VIH (for square wave input) Sinusoidal input amplitude Output duty cycle i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Table 46 lists the timing parameters. CC5 Parameter NOTE is one period or approximately 30 μs. ...

Page 48

... Table 47. Table 50 show the default NFC mode Figure 19, and Table 50 show symmetric Freescale Semiconductor Unit MHz MHz MHz — — — — pdref d µ dck ns mW ...

Page 49

... Setting the data bus pads to Bus-Keeper mode in the IOMUX registers, keeps the data bus valid internally after the specified hold time, allowing proper capturing with slower clock. i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Table 49 Table 49. NFC Clock Settings Examples enfc_clk (MHz) ...

Page 50

... NF5 NF8 NF9 command Figure 14. Command Latch Cycle Timing NF4 NF3 NF10 NF11 NF5 NF7 NF6 NF8 NF9 Address Figure 15. Address Latch Cycle Timing NF3 NF10 NF11 NF5 NF8 NF9 Data to NF Figure 16. Write Data Latch Timing NF2 NF4 Freescale Semiconductor ...

Page 51

... NFIO[15:0] Figure 17. Read Data Latch Timing—Asymmetric Mode NFCE_B NFRE_B NFRB_B NF12 NFIO[15:0] Figure 18. Read Data Latch Timing—Symmetric Mode i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor NF14 NF15 NF13 NF17 NF16 NF12 Data from NF NF14 NF15 ...

Page 52

... Mode Min 2T-1 — T-4.45 — T-1 — 0.5T-5.55 — 0.5T-1.5 — 2T-2.7 — T-4.45 — 0.5T-2.25 — 0.5T-5.55 — T — 0.5T-1.25 — 9T — 0.5T — T — 0.5T-1.5 — 11.2-Tdl — — aclk 2 Tdl 2T +T aclk 13T — 1.5T-3.45 — Freescale Semiconductor ...

Page 53

... Applications Processor Reference Manual (MCIMX51RM) that are the same as those mentioned in this data sheet. Reference Manual WEIM Chapter Nomenclature BCLK CSx WE_B OE_B BEy_B ADV i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Asymmetric Symbol Mode Min tWHR 14T-5.45 tWB ...

Page 54

... EIM_A EIM_A [27:16] [27:16] [27:16] — NANDF_D EIM_DA [7:0] [7:0] — NANDF_D EIM_DA [15:8] [15:8] EIM_D EIM_D — [23:16] [23:16] EIM_D EIM_D — [31:24] [31:24] Freescale Semiconductor 32-Bit (DSZ=011) EIM_DA [15:0] NANDF_D [11:0] EIM_DA [7:0] EIM_DA [15:8] NANDF_D [7:0] NANDF_D [15:8] ...

Page 55

... WE3 BCLK High Level Width WE4 Clock rise to address 3 valid i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor specify the timings related to the WEIM module. All WEIM output WE1 WE2 Figure 20. WEIM Outputs Timing Diagram WE18 WE19 WE20 WE21 Figure 21 ...

Page 56

... Freescale Semiconductor Max 3t+1.75 -t+1.75 3t+1.75 -t+1.75 3t+1.75 -t+1.75 3t+1.75 -t+1.75 3t+1.75 -t+1.75 3t+1.75 -t+1.75 3t+1.75 — — — — ...

Page 57

... ADDR Last Valid Address CSx_B WE_B ADV_B OE_B BEy_B DATA Figure 23. Synchronous Memory, Write Access, WSC=1, WBEA=1, WBEN=1, and WADVN=0 i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor WE4 Address v1 WE6 WE14 WE10 WE12 WE18 WE4 Address V1 WE6 ...

Page 58

... Applications Processors for Consumer and Industrial Products, Rev Address V1 WE14 WE15 WE21 WE20 WE19 D(V1) D(V1+1) Halfword Halfword WE18 Address V1 WE15 WE21 WE20 WE17 D(V2) D(V1) WE16 WE5 Address V2 WE7 WE15 WE11 WE13 D(V2) D(V2+1) Halfword Halfword WE5 WE7 WE9 WE13 WE17 D(V3) D(V4) Freescale Semiconductor ...

Page 59

... CSx_B WE_B WE14 ADV_B OE_B WE12 BEy_B Figure 27. 16-Bit Muxed A/D Mode, Synchronous Read Access, WSC=7, RADVN=1, ADH=1, OEA=2 i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor WE5 WE16 Address V1 WE15 ADVA=1, ADVN=1, and ADH=1 NOTE WE5 Address V1 ...

Page 60

... Applications Processors for Consumer and Industrial Products, Rev Table 54 help to determine timing parameters relative chip select WE31 Address V1 WE39 WE35 WE37 D(V1) WE43 WE31 Address V1 WE33 WE39 WE45 D(V1) WE41 WE32 Next Address WE40 WE36 WE38 WE44 WE32 Next Address WE34 WE40 WE46 WE42 Freescale Semiconductor ...

Page 61

... WE39 CSx_B Valid to ADV_B Valid WE40 ADV_B Invalid to CSx_B Invalid (ADVL is asserted) WE41 CSx_B Valid to Output Data Valid WE42 Output Data Invalid to CSx_B Invalid i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor WE31 Address V1 WE39 WE35 WE37 D(V1) WE43 WE47 Figure 30 ...

Page 62

... Synchronous Measured 1 Parameters MAXCO + MAXDI MAXCO 0 WE12 – WE6 + (WBEA – CSA) WE7 – WE13 + (WBEN – CSN) MAXCO + MAXDTI MAXCO 0 Table 54. Min Max MAXDI — 0 — — (WBEA – CSA) — –3 + (WBEN – CSN MAXDTI — 0 — Freescale Semiconductor Unit ...

Page 63

... Address output hold time 1 This parameter is affected by pad timing. if the slew rate is < 1 V/ns, 0.2 ns should be added to the value. For cmos65 pads this is true for medium and low drive strengths. i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor 55. DD1 DD4 DD3 ...

Page 64

... Freescale Semiconductor Unit ns ns tCK tCK tCK tCK tCK ...

Page 65

... SDRAM CLK and DQS related parameters are being measured from the 50% point. that is, high is defined as 50% of signal value and low is defined as 50% as signal value. DDR SDRAM CLK parameters are measured at the crossing point of SDCLK and SDCLK (inverted clock) i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Table 57. DD25 ...

Page 66

... CS, RAS, CAS, CKE, WE, ODT hold time i.MX51 Applications Processors for Consumer and Industrial Products, Rev DDR4 DDR3 DDR5 DDR4 DDR5 DDR4 DDR7 COL/BA Symbol DDR1 DDR2 SDCLK = 200 MHz Min Max 0.45 0.55 0.45 0.55 5 — 1 0.35 — 1 0.475 — Freescale Semiconductor Unit ...

Page 67

... SDCLK and DQS related parameters are measured from the 50% point. For example, a high is defined as 50% of the signal value and a low is defined as 50% of the signal value. DDR SDRAM CLK parameters are measured at the crossing point of SDCLK and SDCLK_B i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Symbol t IS ...

Page 68

... SDCLK = 200 MHz Symbol Min Max t 0.15 — DS(base) t 0.275 — DH(base) t 0.025 — DS1(base) t 0.025 — DH1(base) t 0.2 — DSS t 0.2 — DSH t –0.25 0.25 DQSS t 0.35 — DQSH t 0.35 — DQSL Freescale Semiconductor Unit tCK tCK tCK tCK tCK ...

Page 69

... SDRAM CLK and DQS related parameters are being measured from the 50% point. that is, high is defined as 50% of signal value and low is defined as 50% as signal value. DDR SDRAM CLK parameters are measured at the crossing point of SDCLK and SDCLK (inverted clock). i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Electrical Characteristics 1 2 ...

Page 70

... Applications Processors for Consumer and Industrial Products, Rev DDR25 DDR24 DATA DATA DATA DATA Table 63. DDR2 SDRAM Read Cycle Parameter DATA DATA DATA DATA 1 2 SDCLK = 200 MHz Symbol Min Max t — 0.35 DQSQ t 1.8 — –0.5 0.5 DQSCK Freescale Semiconductor Unit ...

Page 71

... CS5 SSx Lead Time (Slave Select setup time) CS6 SSx Lag Time (SS hold time) i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor 64. Table 64. CSPI Nomenclature and Routing 1 CSPI1 , USBH1, and DI1 via IOMUX NANDF and USBH1 via IOMUX ...

Page 72

... Table 66 lists the CSPI Slave Mode timing CS2 CS2 Symbol t clk CSLH t SCS t HCS t Smosi t Hmosi = 20 pF) t LOAD PDmiso Min Max Unit – — — — ns CS5 CS6 CS4 Min Max 60 — 26 — 26 — 26 — 26 — 5 — 5 — Freescale Semiconductor Unit ...

Page 73

... Lag Time (CS hold time) CS7 eCSPIx_DO Setup Time CS8 eCSPIx_DO Hold Time CS9 eCSPIx_DI Setup Time CS10 eCSPIx_DI Hold Time CS11 eCSPIx_DRYN Setup Time i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Table 65 CS2 CS3 CS2 CS3 Symbol t t RISE/FALL t CSLH ...

Page 74

... Applications Processors for Consumer and Industrial Products, Rev Table 67 CS2 CS3 CS2 Symbol t clk RISE/FALL t CSLH t SCS t HCS t Smosi t Hmosi t Smiso t Hmiso lists the eCSPI Slave Mode timing CS6 CS5 CS4 Min Max Unit 60 — — — — 15 — 5 — 5 — 5 — 5 — 5 — 5 — Freescale Semiconductor ...

Page 75

... Clock Fall Time eSDHC Output/Card Inputs CMD, DAT (Reference to CLK) 4 SD6 eSDHC Output Delay eSDHC Input / Card Outputs CMD, DAT (Reference to CLK) i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Table 69 lists the eSDHCv2 timing characteristics. SD4 SD2 SD5 MMCx_CLK ...

Page 76

... MII receive channel signal timing Table 70. MII Receive Signal Timing 1 Min Max 2.5 — ISU 5 2.5 — IH – 25 MHz. In high-speed mode, clock – 20 MHz. In high-speed mode, clock Min Max Unit 5 — — ns 35% 65% FEC_RX_CLK period 35% 65% FEC_RX_CLK period Freescale Semiconductor Unit ns ns ...

Page 77

... FEC_TX_EN, FEC_TX_CLK, and FEC_TXD0 have the same timing in 10 Mbps 7-wire interface mode. . FEC_TX_CLK (input) FEC_TXD[3:0] (outputs) FEC_TX_EN FEC_TX_ER Figure 43. MII Transmit Signal Timing Diagram i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Table 71 lists MII transmit channel timing parameters Table 71. MII Transmit Signal Timing 1 ...

Page 78

... Figure 44. MII Async Inputs Timing Diagram Figure 45 Table 73. MII Transmit Signal Timing Characteristic Figure 44 shows MII asynchronous Min Max Unit 1.5 — FEC_TX_CLK period shows MII serial management channel Min Max Unit 0 — — — 0 — 40% 60% FEC_MDC period 40% 60% FEC_MDC period Freescale Semiconductor ...

Page 79

... This section describes the timing parameters of the HS-I following modes: Standard, Fast and High speed. See the errata for the HS-I 2 two standard I C modules that have no errata. i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor M14 M12 M13 Table 74. Table 74. FPM Specifications ...

Page 80

... C-bus specification) Freescale Semiconductor START Unit µ s µ s µ s µ s µ s µ s µ µ ...

Page 81

... IC14 Capacitive load for each bus line ( device must internally provide a hold time of at least 300 ns for SDAH signal in order to bridge the undefined region of the falling edge of SCLH. i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor 2 C module, and IC12 IC11 ...

Page 82

... Freescale Semiconductor 2 C START Unit Max µ — s µ — s µ — µ 0.9 s µ — s µ — s µ — ...

Page 83

... Start of Frame nth frame SENSB_VSYNC SENSB_HSYNC SENSB_PIX_CLK SENSB_DATA[19:0] invalid Figure 49. Gated Clock Mode Timing Diagram i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor cameras, displays, graphics accelerators, and TV encoders. — Active Line n+1th frame invalid 1st byte Electrical Characteristics ...

Page 84

... Applications Processors for Consumer and Industrial Products, Rev n+1th frame 1st byte is that of a typical sensor. Some other sensors may have a slightly IP2 IP3 Figure 51. Sensor Interface Timing Diagram Section 4.7.8.1.2, “Gated Clock Figure 50. All incoming pixel clocks are invalid 1st byte 1/IP1 Freescale Semiconductor Mode”), ...

Page 85

... Data and control holdup time 4.7.8.3 IPU Display Interface Signal Mapping The IPU supports a number of display output video formats. Interface Pins used during various supported video interface formats. i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Electrical Characteristics Symbol Min Fpck 0.01 ...

Page 86

... Groups should not be overlapped. DAT[3] b) The bit order is expressed in DAT[4] each of the bit groups, for example B[0] = least significant blue pixel DAT[5] bit DAT[6] DAT[7] DAT[8] DAT[9] DAT[10] DAT[11] DAT[12] DAT[13] DAT[14] DAT[15] — — — — — — Freescale Semiconductor ...

Page 87

... This mode works in compliance with recommendation ITU-R BT.656. The timing reference signals (frame start, frame end, line start, and line end) are embedded in the 8-bit data bus. Only video data is supported, transmission of non-video related data during blanking intervals is not supported. i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor LCD 18-bit 24-bit ...

Page 88

... Synchronous Interfaces to Standard Active Matrix TFT LCD Panels 4.7.8.5.1 IPU Display Operating Signals The IPU uses four control signals and data to operate a standard synchronous interface: • IPP_DISP_CLK—Clock to display • HSYNC—Horizontal synchronization i.MX51 Applications Processors for Consumer and Industrial Products, Rev NOTE Freescale Semiconductor ...

Page 89

... All shown on the figure parameters are programmable. All controls are started by corresponding i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor LINE 2 LINE 3 ...

Page 90

... IP13 VSYNC HSYNC DRDY IP11 Figure 54. TFT Panels Timing Diagram—Vertical Sync Pulse i.MX51 Applications Processors for Consumer and Industrial Products, Rev IP8o IP8 D0 IP9o IP9 IP6 Start of frame IP14 IP12 IP7 IP5 Dn D1 IP10 End of frame IP15 Freescale Semiconductor ...

Page 91

... IP10 Horizontal blank interval 2 IP12 Screen height IP13 VSYNC width IP14 Vertical blank interval 1 IP15 Vertical blank interval 2 i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Figure 53 Symbol Value 1 Tdicp ( ) Display interface clock. Tdpcp DISP_CLK_PER_PIXEL Time of translation of one pixel to display, × ...

Page 92

... DRDY_OFFSET— offset of DRDY edges from a suitable local start point, when a corresponding data has been set on the × bus, in DI_CLK 2 (0.5 DI_CLK Resolution) The DRDY_OFFSET should be built by suitable DI’s counter. DISP_CLK_PERIOD for integer ------------------------------------------------------ - DI_CLK_PERIOD DISP_CLK_PERIOD for fractional ------------------------------------------------------ - DI_CLK_PERIOD Freescale Semiconductor Unit ...

Page 93

... The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These conditions may be chip specific. i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor ± Accuracy = T 0.75ns ...

Page 94

... The active intervals—during which data is transferred—are marked by the HSYNC signal being high. i.MX51 Applications Processors for Consumer and Industrial Products, Rev × 1 ⎛ 2 DISP_CLK_DOWN × Tdicd = -- - T diclk ceil ------------------------------------------------------------ - ⎝ 2 DI_CLK_PERIOD × ⎛ DISP_CLK_UP × Tdicu = -- - T diclk ceil -------------------------------------------------- - ⎝ 2 DI_CLK_PERIOD 56. NOTE ⎞ ⎠ ⎞ ⎠ Freescale Semiconductor ...

Page 95

... HSYNC DRDY VSYNC Even Field 308 309 HSYNC DRDY VSYNC Odd Field Figure 56. TV Encoder Interface Timing Diagram i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Pixel Data Timing 524 525 Even Field 262 263 264 ...

Page 96

... Degrees 75 — dB 0.8 — ±Degrees 1.5 — ±% –70 — dB –47 — dB 0.5 — ±Degrees 2.5 — ±% 0.1 — ±% Freescale Semiconductor ...

Page 97

... A pause between two different display accesses can be guaranteed by programing of suitable access sizes. There are no minimal/maximal hold/setup time hard defined by DI. Each control signal can be switched at any time during access size. i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor — — — ...

Page 98

... Single access mode (all control signals are not active for one display interface clock after each display access) Figure 57. Asynchronous Parallel System 80 Interface (Type 1) Timing Diagram i.MX51 Applications Processors for Consumer and Industrial Products, Rev Burst access mode with sampling by CS signal Freescale Semiconductor ...

Page 99

... WR RD IPP_DATA Single access mode (all control signals are not active for one display interface clock after each display access) Figure 58. Asynchronous Parallel System 80 Interface (Type 2) Timing Diagram i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Electrical Characteristics 99 ...

Page 100

... Single access mode (all control signals are not active for one display interface clock after each display access) Figure 59. Asynchronous Parallel System 68k Interface (Type 1) Timing Diagram i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 100 Burst access mode with sampling by CS signal Freescale Semiconductor ...

Page 101

... Display operation can be performed with IPP_WAIT signal. The DI reacts to the incoming IPP_WAIT signal with 2 DI_CLK delay. The DI finishes a current access and a next access is postponed until IPP_WAIT release. i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Burst access mode with sampling by ENABLE signal Electrical Characteristics 101 ...

Page 102

... Electrical Characteristics Figure 61 shows timing of the parallel interface with IPP_WAIT control. DI clock IPP_CS IPP_DATA WR RD IPP_WAIT IPP_DATA_IN IP39 Figure 61. Parallel Interface Timing Diagram—Read Wait States i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 102 waiting waiting Freescale Semiconductor ...

Page 103

... Read system cycle time IP28a Address Write system cycle time Tcycwa IP28d Data Write system cycle time IP29 RS start IP30 CS start IP31 CS hold i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor IP36 IP34 D1 IP28d Symbol Value Tcycr ACCESS_SIZE_# ACCESS_SIZE_# Tcycwd ACCESS_SIZE_# ...

Page 104

... Point of input data sampling by DI, predefined in DC Microcode 1 Typ Max 2 Tdicpr+1.5 3 Tdicpw+1.5 Tdicurs+1.5 Tdicucs+1 –Tdicucs Tdicdcs–Tdicucs+1 –Tdicurs Tdicdrs–Tdicurs+1.5 Tdicur+1 –Tdicur Tdicdr–Tdicur+1.5 Tdicuw+1 –Tdicuw Tdicdw–Tdicuw+1 — Tdrp –Tlbd –Tdicur–1.5 — Tdicpr–Tdicdr–1.5 Freescale Semiconductor Unit — — Unit ...

Page 105

... Tdicdrs DISP_DOWN is predefined in REGISTER 7 Display control up for RS DISP_UP is predefined in REGISTER 8 Display control down for read Tdicdr DISP_DOWN is predefined in REGISTER i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Symbol Min Tswait — Tdrp Tdrp–1.5 Tdrp DI_ACCESS_SIZE_# × Tdicpr ...

Page 106

... DISP_UP_# × Tdicur = -- - T DI_CLK ceil ---------------------------------------------- - ⎝ 2 DI_CLK_PERIOD × ⎛ DISP_DOWN_# × ceil ---------------------------------------------------- - ⎝ DI_CLK 2 DI_CLK_PERIOD × ⎛ DISP_UP_# × Tdicuw = -- - T DI_CLK ceil ---------------------------------------------- - ⎝ 2 DI_CLK_PERIOD DISP#_READ_EN × Tdrp = T ceil ------------------------------------------------ - DI_CLK DI_CLK_PERIOD ⎞ ⎠ ⎞ ⎠ ⎞ ⎠ Freescale Semiconductor ...

Page 107

... DISPB_D#_CS delay DISPB_SD_D_CLK DISPB_SD_D (Output) DISPB_SD_D (Input) programed DISPB_D#_CS delay DISPB_SD_D_CLK DISPB_SD_D (Output) DISPB_SD_D (Input) Figure 64. 4-Wire Serial Interface Timing Diagram i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Preamble Write Preamble Read RW RS Preamble D7 Electrical Characteristics programed ...

Page 108

... DISPB_SD_D (Input) programed DISPB_SER_RS delay Figure 65. 5-Wire Serial Interface Timing Diagram i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 108 Write programed delay RW D7 Preamble Read programed delay RW Preamble D7 programed delay Output data programed delay Input data Freescale Semiconductor ...

Page 109

... IP48 Read system cycle time IP49 Write system cycle time IP50 Read clock low pulse width IP51 Read clock high pulse width Trh i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Table 85 shows timing characteristics at display access IP73 IP72 ...

Page 110

... Tdicpw–Tdicdw — — Tdrp –Tlbd -Tdicur-1.5 — Tdicpr-Tdicdr-1.5 Tdicdw — Tdicpw-Tdicdw — Tdicpr Tdicpr+1.5 Tdicpw Tdicpw+1.5 Tdicdr Tdicdr+1.5 Tdicur Tdicur+1.5 Tdicdw Tdicdw+1.5 Tdicuw Tdicuw+1.5 Tdrp Tdrp+1.5 Toclk Toclk+1.5 Tdicurs Tdicurs+1.5 Tdicdrs Tdicdrs+1.5 Tdicucs Tdicucs+1.5 Tdicdcs Tdicdcs+1.5 Freescale Semiconductor Unit ...

Page 111

... Display interface clock offset value CLK_OFFSET is predefined in REGISTER 12 Display RS up time DISP_RS_UP is predefined in REGISTER 13 Display RS down time DISP_RS_DOWN is predefined in REGISTER 14 Display RS up time DISP_CS_UP is predefined in REGISTER i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor × 1 ⎛ 2 DISP_DOWN_# × DI_CLK ceil ---------------------------------------------------- - ⎝ ...

Page 112

... OW6 OW5 Symbol t WR0_low t SLOT DS2502 Tx “Presence Pulse” OW2 OW4 Min Typ Max 480 511 — 15 — — 240 480 512 — Min Typ Max 60 100 120 OW5 117 120 Freescale Semiconductor Unit µs µs µs µs Unit µs µs ...

Page 113

... The selected clock signal is passed through a prescaler before being input to the counter. The output is available at the pulse-width modulator output (PWMO) external pin. i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Figure 70 depicts the Read Sequence timing, and OW8 ...

Page 114

... Applications Processors for Consumer and Industrial Products, Rev. 4 114 Table 89 lists the PWM timing parameters Figure 71. PWM Timing Table 89. PWM Output Timing Parameter Min 1 0 12.29 9.91 — — — 8. Max Unit ipg_clk MHz — ns — ns 0.5 ns 0.5 ns 9.37 ns — ns Freescale Semiconductor ...

Page 115

... In the timing equations, some timing parameters are used. These parameters depend on the implementation of the i.MX51 P-ATA interface on silicon, the bus buffer used, the cable delay and cable skew. i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor SI2 Parameter 1 – ...

Page 116

... Applications Processors for Consumer and Industrial Products, Rev. 4 116 Table 91. P-ATA Timing Parameters Description UDMA2, UDMA3 UDMA0, UDMA1, UDMA2, UDMA3, UDMA4 Value/ 1 Contributing Factor Peripheral clock frequency UDMA0 15 ns UDMA1 UDMA4 5 ns 5.0 ns 12.0 ns 8.5 ns 8 Transceiver Transceiver Transceiver Cable Cable Cable Cable Cable Freescale Semiconductor ...

Page 117

... Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Table 92 lists the timing parameters for PIO read. Figure 73. PIO Read Timing Diagram Table 92. PIO Read Timing Parameters Value × ...

Page 118

... T – (tskew1 + tskew2 + tskew5) × T – (tskew1 + tskew2 + tskew6) × T – (tskew1 + tskew2 +tskew5) × T – tskew1 × T – (tco + tsui + tcable2 + tcable2 + 2 × T Controlling Variable time_1 time_2w time_9 If not met, increase time_2w time_4 × tbuf) time_ax time_1, time_2r, time_9 — — Freescale Semiconductor ...

Page 119

... Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Figure 76 shows timing for MDMA write, and Figure 75. MDMA Read Timing Diagram Figure 76. MDMA Write Timing Diagram Value × T – (tskew1 + tskew2 + tskew5) × ...

Page 120

... Applications Processors for Consumer and Industrial Products, Rev. 4 120 Value × T – (tskew1 + tskew2 + tskew6) × T – tskew1 × T – tskew1 Figure 78 shows timing when the UDMA in device terminates transfer, and Controlling Variable time_jn — shows timing when the UDMA in Freescale Semiconductor ...

Page 121

... There is a special timing requirement in the ATA host that requires the internal DIOW to go only high 3 clocks after the last active edge on the DSTROBE signal. The equation given on this line tries to capture this constraint. 2 Make ton and toff big enough to avoid bus contention. i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Description × T) – (tskew1 + tskew2) × ...

Page 122

... Figure 80. UDMA Out Transfer Starts Timing Diagram Figure 81. UDMA Out Host Terminates Transfer Timing Diagram i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 122 Figure 81 shows timing when the UDMA out device terminates transfer, and shows timing when the UDMA out Freescale Semiconductor ...

Page 123

... Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Value × T) – (tskew1 + tskew2) × T) – (tskew1 + tskew2) × (tskew1 + tskew2) × T) – (tskew1 + tskew2) × ...

Page 124

... Applications Processors for Consumer and Industrial Products, Rev. 4 124 Symbol freq 2 S rise 3 S fall S trans Tr/ Tr/Tf 1/SI1 SI3 SI2 Figure 83. SIM Clock Timing Diagram Min Max 0.01 25 × — 0.09 (1/S ) freq × — 0.09 (1/S ) freq 10 25 — 1 — 1 Freescale Semiconductor Unit MHz µ s µ s ...

Page 125

... SIMx_RSTy is set High (time T1) • SIMx_RSTy must remain High for at least 40000 clock cycles after T1 and a response must be received on SIMx_DATAy_RX_TX between 400 and 40000 clock cycles after T1. i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor response 2 400 clock cycles < Figure ...

Page 126

... SIMx_RSTy goes Low • SIMx_CLKy goes Low • SIMx_DATAy_RX_TX goes Low • SIMx_SVENy goes Low i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 126 400 clock cycles < 400000 clock cycles < response 3 < 200 clock cycles 1 < 40000 clock cycles 2 3 Freescale Semiconductor ...

Page 127

... SIM reset to SIM clock stop SI8 SIM reset to SIM TX data low SI9 SIM reset to SIM voltage enable low SI10 SIM presence detect to SIM reset low i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Figure 86 and SI7 SI8 SI9 Symbol Min × ...

Page 128

... Applications Processors for Consumer and Industrial Products, Rev. 4 128 Figure 88 depicts the SJC boundary scan timing. SJ1 SJ2 VM VIH VIL Figure 87. Test Clock Input Timing Diagram SJ4 Input Data Valid SJ6 Output Data Valid SJ7 SJ6 Output Data Valid Table 99. SJ2 VM SJ3 VIH SJ5 Freescale Semiconductor ...

Page 129

... SJ6 TCK low to output data valid SJ7 TCK low to output high impedance SJ8 TMS, TDI data set-up time i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor SJ8 Input Data Valid SJ10 Output Data Valid SJ11 SJ10 Output Data Valid SJ13 Figure 90 ...

Page 130

... External—EIM or CSPI1 I/O via IOMUX AUD5 External—EIM or SD1 I/O via IOMUX All Frequencies Min Max 25 — — 44 — 44 100 — 40 — All Frequencies Unit Min Max — 1.5 — 24.2 ns — 31.3 — 1.5 — 13.6 ns — 18.0 Type and Access Freescale Semiconductor Unit ...

Page 131

... TXD (Output) RXD (Input) Note: SRXD input in synchronous mode only Figure 91. SSI Transmitter Internal Clock Timing Diagram i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Signal Nomenclature AUD6 External—EIM or DISP2 via IOMUX SSI 3 Internal NOTE Table 102 ...

Page 132

... Synchronous Internal Clock Operation NOTE Min Max Unit 81.4 — ns 36.0 — ns — 6.0 ns 36.0 — ns — 6.0 ns — 15.0 ns — 15.0 ns — 15.0 ns — 15.0 ns — 6.0 ns — 6.0 ns — 15.0 ns — 15.0 ns — 15.0 ns — 6 — ns 0.0 — ns — 25.0 pF Freescale Semiconductor ...

Page 133

... CK high to FS (wl) high SS13 (Rx) CK high to FS (wl) low SS20 SRXD setup time before (Rx) CK low SS21 SRXD hold time after (Rx) CK low i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Table 103 SS1 SS5 SS4 SS9 SS11 SS20 ...

Page 134

... For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation). i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 134 Parameter Oversampling Clock Operation NOTE Min Max Unit 15.04 — ns 6.0 — ns — 3.0 ns 6.0 — ns — 3.0 ns Freescale Semiconductor ...

Page 135

... CK high to FS (wl) high SS33 (Tx) CK high to FS (wl) low SS37 (Tx) CK high to STXD valid from high impedance SS38 (Tx) CK high to STXD high/low i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Table 104 SS22 SS25 SS26 SS27 SS29 SS31 ...

Page 136

... For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation). i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 136 Parameter Synchronous External Clock Operation NOTE Min Max Unit — 15.0 ns 10.0 — ns 2.0 — ns — 6.0 ns Freescale Semiconductor ...

Page 137

... External FS rise time SS36 (Tx/Rx) External FS fall time SS40 SRXD setup time before (Rx) CK low SS41 SRXD hold time after (Rx) CK low i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Table 105 SS22 SS26 SS25 SS28 SS30 SS32 ...

Page 138

... Output Input DCE Mode Description RTS from DTE to DCE CTS from DCE to DTE DTR from DTE to DCE DSR from DCE to DTE DCD from DCE to DTE RING from DCE to DTE Serial data from DCE to DTE Serial data from DTE to DCE Freescale Semiconductor ...

Page 139

... Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16. baud_rate 4.7.16.1.2 UART IrDA Mode Timing The following subsections give the UART transmit and receive timings in IrDA mode. i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Symbol Min 1 t 1/F ...

Page 140

... But accumulation tolerance in one frame must baud_rate Table 109 Max Units 1/F +T — baud_rate ref_clk (3/16)×(1F )+T — baud_rate ref_clk Table 110 Max Units 1/F + — baud_rate 1/(16×F ) baud_rate (5/16)×(1/F ) — baud_rate Freescale Semiconductor lists lists ...

Page 141

... I/O int data(3) Out i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Parameters.” Description Active high transmit enable Transmit differential data on D+/D– Transmit single-ended zero on D+/D– Active high interrupt indication Must be asserted whenever any unmasked interrupt occurs Single-ended receive data from D+ Single-ended receive data from D– ...

Page 142

... Transmit enable, active low Out TX data when USB_TXOE_B is low In Differential RX data when USB_TXOE_B is high Out SE0 drive when USB_TXOE_B is low In SE0 RX indicator when USB_TXOE_B is high US1 US4 US7 Figure 99 shows the USB Signal Description US3 US2 Table 114 shows the US8 Freescale Semiconductor ...

Page 143

... USB transmit/receive waveform in DAT_SE0 uni-directional mode respectively. Transmit USB_TXOE_B USB_DAT_VP USB_SE0_VM Figure 101. USB Transmit Waveform in DAT_SE0 Uni-directional Mode i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Signal Name Direction Min Out — Out — Out — ...

Page 144

... TX VP data when USB_TXOE_B is low In (Rx data when USB_TXOE_B is high Out (Tx data when USB_TXOE_B low In (Rx data when USB_TXOE_B high In Differential RX data US16 Condition/ Max Unit Reference Signal 51.0 % — Figure 103 and Figure 104 shows Signal Description Freescale Semiconductor ...

Page 145

... US18 TX Rise/Fall Time USB_DAT_VP US19 TX Rise/Fall Time USB_SE0_VM US20 TX Rise/Fall Time USB_TXOE_B US21 TX Duty Cycle USB_DAT_VP US22 TX Overlap USB_SE0_VM i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor US18 US22 US26 US28 US29 Direction Min Max Out — 5.0 Out — ...

Page 146

... TX VP data when USB_TXOE_B is low Out TX VM data when USB_TXOE_B is low data when USB_TXOE_B is high data when USB_TXOE_B is high In Differential RX data US30 US34 Unit Condition/Reference Signal 3 3 4.0 ns USB_SE0_VM 2.0 ns USB_DAT_VP Figure 105 and Figure 106 Signal Description US32 US31 US34 Freescale Semiconductor ...

Page 147

... US33 TX Duty Cycle USB_DAT_VP US34 TX Overlap USB_SE0_VM US38 RX Rise/Fall Time US39 RX Rise/Fall Time USB_VM1 US40 RX Skew US41 RX Skew USB_RCV i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor US38 US40 US39 US41 Signal Direction Min Max Out — Out — ...

Page 148

... Stop. The link asserts this signal for 1 clock cycle to stop the data stream currently on the bus. In Next. The PHY asserts this signal to throttle the data. US16 US16 US17 Parameter 1 Table 122 shows the USB timing Signal Description US17 Conditions/ Min Max Unit Reference Signal 6 — — — — Freescale Semiconductor ...

Page 149

... USB PHY system clocking parameters. Table 125. USB PHY System Clocking Parameters Parameter Conditions Clock deviation — Rise/fall time — i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Table 123. USB PHY AC Timing Parameters Min Typ 75 — 4 0.5 75 — ...

Page 150

... Applications Processors for Consumer and Industrial Products, Rev. 4 150 Min Typ VBUS Table 126. Comparators Thresholds Conditions Min — 0.8 — 0.8 — 0.2 — 4.4 Max — 50 — 100 — 60 Typ Max 1.4 2.0 1.4 4.0 0.45 0.8 4.6 4.75 Freescale Semiconductor Unit Unit ...

Page 151

... Package Drawing Notes The following notes apply to Figure 1 All dimensions in millimeters. 2 Dimensioning and tolerancing per ASME Y14.5M-1994. 3 Maximum solder ball diameter measured parallel to Datum A. i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Package Information and Contact Assignments 108. 151 ...

Page 152

... NVCC_EMI_DRAM L5, M5, R5, T5, Y5, AA5 NVCC_HS10 M20 NVCC_HS4_1 L20 NVCC_HS4_2 P20 NVCC_HS6 N20 NVCC_I2C V11 NVCC_IPU2 V20 NVCC_IPU4 N16 NVCC_IPU5 K16 NVCC_IPU6 M16 i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 152 displays an alpha-sorted list of the signal assignments. Contact Assignment Table 129 Freescale Semiconductor ...

Page 153

... N12, N14, N15, P12, P13, P14, P15, R13, R14, R15, T14, T15, T16, U14, U15, U16 VDD_ANA_PLL_A AD4 VDD_ANA_PLL_B AC24 VDD_DIG_PLL_A AD3 VDD_DIG_PLL_B AB23 VDD_FUSE P6 i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Package Information and Contact Assignments Contact Assignment 153 ...

Page 154

... Input 100 kΩ pull-up Input 100 kΩ pull-up Input Analog Input Analog Input Standard CMOS Input 100 kΩ pull-up Input Analog Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Freescale Semiconductor ...

Page 155

... DI_GP3 H23 DI_GP4 K23 DI1_D0_CS W20 DI1_D1_CS T18 DI1_DISP_CLK J22 DI1_PIN11 V18 i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Package Information and Contact Assignments I/O Buffer Power Rail Type NVCC_HS10 HSGPIO NVCC_PER8 GPIO NVCC_PER8 GPIO NVCC_PER8 GPIO ...

Page 156

... Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Freescale Semiconductor ...

Page 157

... DRAM_A1 V3 DRAM_A10 T4 DRAM_A11 R1 DRAM_A12 P2 DRAM_A13 R4 DRAM_A14 R2 DRAM_A2 U4 DRAM_A3 U3 i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Package Information and Contact Assignments I/O Buffer Power Rail Type NVCC_IPU4 GPIO NVCC_IPU8 GPIO NVCC_IPU8 GPIO NVCC_IPU9 GPIO NVCC_IPU9 GPIO NVCC_IPU9 GPIO ...

Page 158

... High Output High Output High Output High Output High Output High Output High Output High Output High Output High Output High Output High Output High Output High Output High Output High Output High Output High Output High Output High Freescale Semiconductor ...

Page 159

... EIM_A16 Y12 1 EIM_A17 AE6 1 EIM_A18 Y13 1 EIM_A19 AE7 1 EIM_A20 Y6 i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Package Information and Contact Assignments I/O Buffer Power Rail Type NVCC_EMI_DRAM DDR2 NVCC_EMI_DRAM DDR2 NVCC_EMI_DRAM DDR2 NVCC_EMI_DRAM DDR2 NVCC_EMI_DRAM DDR2 NVCC_EMI_DRAM ...

Page 160

... Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Freescale Semiconductor ...

Page 161

... K6 EIM_SDODT0 L2 EIM_SDODT1 L3 EIM_WAIT AB6 EXTAL AD23 FASTR_ANA AE22 FASTR_DIG AC21 i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Package Information and Contact Assignments I/O Buffer Power Rail Type NVCC_EMI GPIO NVCC_EMI GPIO NVCC_EMI GPIO NVCC_EMI GPIO NVCC_EMI GPIO ...

Page 162

... Output — Input/ 47 kΩ pull-up Open-drain output Input 100 kΩ pull-down Input 100 kΩ pull-down Input 47 kΩ pull-up 3-state output Keeper Input 47 kΩ pull-up Input 47 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Freescale Semiconductor ...

Page 163

... NANDF_D14 E4 NANDF_D15 J6 NANDF_D2 C6 NANDF_D3 B5 NANDF_D4 B6 NANDF_D5 F8 NANDF_D6 A6 NANDF_D7 A5 i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Package Information and Contact Assignments I/O Buffer Power Rail Type NVCC_PER13 GPIO NVCC_PER13 GPIO NVCC_PER13 GPIO NVCC_PER13 GPIO NVCC_PER13 GPIO NVCC_PER13 GPIO ...

Page 164

... Input 47 kΩ pull-up Input 47 kΩ pull-up Input 360 kΩ pull-down Output — Input 47 kΩ pull-up Input 47 kΩ pull-up Input 47 kΩ pull-up Input 47 kΩ pull-up Input 360 kΩ pull-down — — Freescale Semiconductor ...

Page 165

... During power-on reset this port acts as output for diagnostic signal. See 5.1.2 Connect Assignments Table 129 shows the device No Connect assignment list. Table 129 Connect Assignments Ball Status i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Power Rail NVCC_PER3 NVVCC_PER12 NVVCC_PER12 NVVCC_PER12 NVVCC_PER12 NVVCC_PER12 ...

Page 166

... Ball Status i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 166 Ball Assignments E11 E12 E14 E15 E17 E18 E20 E21 F5 F21 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G21 H5 H7 H17 H19 H21 J5 J7 Freescale Semiconductor ...

Page 167

... Table 129 Connect Assignments (continued) Ball Status i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Ball Assignments Package Information and Contact Assignments J17 J19 J21 K7 K17 K19 K21 L7 L17 L19 M7 M17 M19 M21 N7 N17 N19 N21 P5 P7 P17 ...

Page 168

... Ball Status i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 168 Ball Assignments V19 V21 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W21 Y21 AA6 AA8 AA9 AA11 AA12 AA14 AA15 AA17 AA18 AA20 AA21 Freescale Semiconductor ...

Page 169

... See 5 Package Information This section contains the outline drawing, signal assignment map, ground/power/reference ID (by ball grid location) for the 19 × 19 mm, 0.8 mm pitch package. i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Package Information and Contact Assignments 169 ...

Page 170

... Package Information and Contact Assignments 5.2.1 BGA—Case 2017 mm, 0.8 mm Pitch shows the top view, bottom view, and side view of the 19 ×19 mm package. Figure 109 Figure 109 Package: Case 2017-01—0.8 mm Pitch i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 170 Freescale Semiconductor ...

Page 171

... H6, J6, K6, L6, M6, N6, P6, R6, T6 NVCC_HS10 M16 NVCC_HS4_1 M18 NVCC_HS4_2 N18 NVCC_HS6 M17 NVCC_I2C T14 i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Package Information and Contact Assignments 109. Table 131 displays an alpha-sorted list of the signal Contact Assignment 171 ...

Page 172

... SGND J11 SVCC H14 SVDDGP F13 TVDAC_DHVDD V16 VBUS K20 VCC H13, J15, J16, K15, K16, L7, L15, M7, N7, N17, P7, P17, R17, T8, T9, T10, T11, T12, T17 VDD_ANA_PLL_A V6 i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 172 Contact Assignment Freescale Semiconductor ...

Page 173

... Y17 CSI1_D10 R22 CSI1_D11 R23 CSI1_D12 P22 CSI1_D13 P23 CSI1_D14 M20 i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Package Information and Contact Assignments Contact Assignment Power Rail I/O Buffer Type NVCC_PER9 GPIO NVCC_PER9 GPIO NVCC_PER9 GPIO NVCC_PER9 ...

Page 174

... Keeper Input Keeper Input Keeper Input 100 kΩ pull-up Input 100 kΩ pull-up Input Keeper Input 100 kΩ pull-up Input 100 kΩ pull-up Input 100 kΩ pull-up Input Keeper Input Keeper Input 100 kΩ pull-up Input 100 kΩ pull-up Freescale Semiconductor ...

Page 175

... DISP1_DAT21 H19 2 DISP1_DAT22 F22 2 DISP1_DAT23 G21 DISP1_DAT3 U23 DISP1_DAT4 T22 i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Package Information and Contact Assignments Power Rail I/O Buffer Type NVCC_IPU2 GPIO NVCC_IPU2 GPIO NVCC_IPU6 GPIO NVCC_IPU2 GPIO NVCC_IPU2 GPIO ...

Page 176

... Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Output High Input 100 kΩ pull-up Input 100 kΩ pull-up Output High Output – Output – Output High Output High Output High Output High Output High Freescale Semiconductor ...

Page 177

... K1 DRAM_D2 R2 DRAM_D20 K3 DRAM_D21 K4 DRAM_D22 J3 DRAM_D23 J4 DRAM_D24 K5 DRAM_D25 H1 i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Package Information and Contact Assignments Power Rail I/O Buffer Type NVCC_EMI_DRAM DDR2 NVCC_EMI_DRAM DDR2 NVCC_EMI_DRAM DDR2 NVCC_EMI_DRAM DDR2 NVCC_EMI_DRAM DDR2 NVCC_EMI_DRAM DDR2 NVCC_EMI_DRAM ...

Page 178

... High Output High Output High Output High Output High Output High Output High Output High Output High Output High Output High Output High Output High Output High Output High Output High Output High Output High Input 100 kΩ pull-up Freescale Semiconductor ...

Page 179

... AC11 EIM_D23 V8 EIM_D24 AA10 EIM_D25 Y9 EIM_D26 AB10 EIM_D27 W8 EIM_D28 AC10 i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Package Information and Contact Assignments Power Rail I/O Buffer Type NVCC_EMI GPIO NVCC_EMI GPIO NVCC_EMI GPIO NVCC_EMI GPIO NVCC_EMI GPIO ...

Page 180

... Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input 100 kΩ pull-up Output High Output High Input Keeper Input Keeper Output High Output High Output High Output High Output High Output High Output High Output High Freescale Semiconductor ...

Page 181

... AB15 JTAG_MOD V14 JTAG_TCK V15 JTAG_TDI Y14 JTAG_TDO AA15 JTAG_TMS AC16 i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Package Information and Contact Assignments Power Rail I/O Buffer Type NVCC_EMI GPIO NVCC_OSC Analog NVCC_PER3 — NVCC_PER3 — NVCC_USBPHY ...

Page 182

... High Output High Output High Output High Output High Output Low Output Low Output Low Output Low Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Freescale Semiconductor ...

Page 183

... B18 SD2_CMD G17 SD2_DATA0 E17 SD2_DATA1 B19 SD2_DATA2 D17 SD2_DATA3 C17 i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Package Information and Contact Assignments Power Rail I/O Buffer Type NVCC_NANDF_C UHVIO NVCC_NANDF_C UHVIO NVCC_NANDF_B UHVIO NVCC_NANDF_B UHVIO NVCC_NANDF_B ...

Page 184

... Input 100 kΩ pull-up Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Input Keeper Output — for details for details Freescale Semiconductor ...

Page 185

... EIM_A21 Input 100 kΩ pull-up EIM_A23 Input 100 kΩ pull-up KEY_COL3 Output i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Table 132. Fuse Override Contacts Signal Configuration After Reset Keeper BT_SPARE_SIZE Keeper BT_LPB_FREQ[2] Keeper BT_MLC_SEL ...

Page 186

... Applications Processors for Consumer and Industrial Products, Rev. 4 186 Signal Configuration After Reset Low Output for diagnostic signal ANY_PU_RST during power-on reset Low Output for diagnostic signal JTAG_ACT during power-on reset 1 External Termination for Fuse Override — — Freescale Semiconductor ...

Page 187

... CSPI1_RDY AUD3_BB_RXD 8 CSI2_D18 AUD3_BB_TXD 7 NANDF_D6 6 NANDF_D7 5 NANDF_D8 4 NANDF_D12 3 NANDF_CS6 2 GND 1 i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor GND GPIO1_9 DISP1_DAT6 GPIO1_6 GPIO1_8 DISP1_DAT7 GPIO1_2 DISP1_DAT8 DISP1_DAT9 GPIO1_4 GPIO1_5 DISP1_DAT14 SD2_DATA1 GPIO1_1 CSI2_PIXCLK CSI1_D9 CSI2_VSYNC NVCC_PER5 CSI1_VSYNC CSI1_HSYNC ...

Page 188

... NVCC_HS4_1 NVCC_HS10 20 — — 19 DISP2_DAT8 DISP2_DAT12 18 — — 17 NVCC_IPU9 NVCC_IPU6 16 GND GND 15 GND GND 14 GND GND 13 VDDGP GND 12 VDDGP SVDDGP 11 VDDGP VDDGP 10 VDDGP VDDGP VDDGP VDDGP — — VDDGP VDDGP NVCC_EMI_DRAM EIM_SDBA1 DRAM_DQM2 EIM_SDODT1 DRAM_SDWE EIM_SDODT0 DRAM_SDCLK_B DRAM_SDCLK Freescale Semiconductor ...

Page 189

... GND — 5 DRAM_CAS EIM_SDBA0 4 DRAM_RAS DRAM_CS0 3 DRAM_DQM3 DRAM_A12 2 DRAM_SDCKE0 DRAM_A9 1 i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Package Information and Contact Assignments CSI1_D11 DISP1_DAT3 CSI1_D10 DISP1_DAT2 DISP1_DAT4 DISP1_DAT0 DISP1_DAT5 DISP1_DAT1 — — DISP2_DAT6 DISP2_DAT0 — — DISP2_DAT10 DI1_D1_CS — ...

Page 190

... GND EIM_A26 — EIM_WAIT NVCC_EMI_DRAM EIM_LBA DRAM_D5 DRAM_D3 DRAM_D4 DRAM_D2 DRAM_D10 DRAM_D12 DRAM_D11 DRAM_D13 GND_ANA_PLL_B 25 VDD_ANA_PLL_B 24 NGND_OSC 23 NVCC_TV_BACK 22 FASTR_DIG 21 COMP 20 PMIC_RDY 19 PMIC_INT_REQ 18 JTAG_TMS 17 JTAG_DE_B 16 EIM_DA2 15 EIM_DA7 14 EIM_DA10 13 EIM_DA14 12 EIM_EB3 11 EIM_D19 10 EIM_D25 9 EIM_D30 8 EIM_CS4 7 EIM_A27 6 EIM_DTACK 5 DRAM_D0 4 DRAM_D1 3 DRAM_D14 2 DRAM_D15 1 Freescale Semiconductor ...

Page 191

... EIM_DA13 EIM_DA11 12 EIM_DA15 EIM_D22 11 EIM_D20 EIM_D21 10 EIM_D18 EIM_D24 9 EIM_D26 EIM_D17 8 EIM_D29 EIM_A19 7 EIM_A21 EIM_A17 6 EIM_A25 EIM_A23 5 VDD_ANA_PLL_A EIM_CS2 4 VDD_DIG_PLL_A GND_ANA_PLL_A 3 GND GND_DIG_PLL_A 2 GND GND 1 i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Package Information and Contact Assignments 191 ...

Page 192

... DISP1_DAT13 20 CSI2_PIXCLK CSI2_VSYNC 19 CSI1_D8 CSI1_PIXCLK 18 SD2_DATA0 SD1_DATA2 17 SD1_CMD KEY_COL4 16 KEY_COL0 KEY_ROW2 15 OWIRE_LINE UART3_RXD 14 UART1_RXD SVDDGP 13 USBH1_DATA0 VDDGP 12 USBH1_STP VDDGP 11 CSPI1_SS0 VDDGP 10 AUD3_BB_TXD VDDGP 9 NANDF_D1 VDDGP 8 NANDF_D9 VDDGP 7 NVCC_NANDF_A VDDGP 6 NANDF_CS6 NVCC_NANDF_A 5 NANDF_CS2 NANDF_CLE 4 NANDF_ALE EIM_SDODT0 3 NANDF_RE_B EIM_SDODT1 2 NANDF_WE_B EIM_SDBA2 1 Freescale Semiconductor ...

Page 193

... NVCC_EMI_DRAM 6 GND DRAM_DQM3 5 DRAM_D31 DRAM_SDQS3_B 4 DRAM_D30 DRAM_SDQS3 3 DRAM_D29 DRAM_D26 2 DRAM_D28 DRAM_D25 1 i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Package Information and Contact Assignments GPANAIO DP DI_GP4 DN DI2_DISP_CLK VREG DI2_PIN2 VBUS DI_GP2 RREFEXT DI1_DISP_CLK DI2_PIN3 NVCC_IPU6 NVCC_IPU7 VCC VCC ...

Page 194

... POR_B 20 DISP2_DAT13 DISPB2_SER_DIN 19 NVCC_IPU2 NVCC_PER3 18 VCC GND_ANA_PLL_B 17 GND NVCC_TV_BACK 16 NGND_TV_BACK VREFOUT 15 NVCC_I2C NVCC_SRTC_POW 14 VDDA NVCC_PER14 13 VCC NVCC_EMI 12 VCC NVCC_EMI 11 VCC NVCC_EMI 10 VCC NVCC_EMI 9 VCC NVCC_EMI 8 GND_DIG_PLL_A GND_ANA_PLL_A 7 NVCC_EMI_DRAM VDD_DIG_PLL_A 6 GND DRAM_SDWE 5 DRAM_SDCLK_B DRAM_A11 4 DRAM_SDCLK EIM_SDBA1 3 DRAM_A14 DRAM_A12 2 DRAM_D0 DRAM_A13 1 Freescale Semiconductor ...

Page 195

... DRAM_A3 DRAM_SDCKE1 5 DRAM_CAS DRAM_A4 4 DRAM_A9 DRAM_A6 3 DRAM_A10 DRAM_A8 2 EIM_SDBA0 DRAM_RAS 1 i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Package Information and Contact Assignments DISP2_DAT12 DISP2_DAT14 DI1_D1_CS DI1_PIN11 DI1_PIN12 BOOT_MODE1 RESET_IN_B CLK_SS BOOT_MODE0 FASTR_DIG CKIH2 EXTAL AHVSSRGB AHVSSRGB IOB_BACK ...

Page 196

... In the VIH Parameters” after Table Table 50. Table 82. 132, under the 133, under the Internal 135, under the External Electrical”, under Section 4.7.16, “UART”. 147, for 148, added an Table 1, Table 13, "i.MX51 Operating Ranges," on Freescale Semiconductor 12. 49. 145, ...

Page 197

... Removed table footenote in Consumption," on page • Removed table footnote in page • Updated i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor Substantive Change(s) Table 15, "Fuse Supply Current," on page 25. Table 19, "DDR2 I/O DC Electrical Parameters," on page 27. ...

Page 198

... THIS PAGE INTENTIONALLY LEFT BLANK i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 198 Freescale Semiconductor ...

Page 199

... THIS PAGE INTENTIONALLY LEFT BLANK i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4 Freescale Semiconductor 199 ...

Page 200

... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...

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