MCIMX515DJM8C Freescale, MCIMX515DJM8C Datasheet - Page 196

• Manufacturer Part Number: MCIMX515DJM8C
• Manufacturer: Freescale

Specifications of MCIMX515DJM8C

• Operating Temperature (min): -20C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Revision History
6
Table 135
196
2
Number
Rev.
1
2
Revision History
provides a revision history for this data sheet.
10/30/2009
05/28/2010
Date
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4
Table 135. i.MX51 Data Sheet Document Revision History
Initial public release.
• Changed the VREFOUT column in
• Added
• Updated
• Added a note in
• Updated
• Changed the Input current (47 kΩ Pull-up) coulmn in
• Added new table for parameters for DDR2 Pad output buffer Impedance. Refer to
• Added new section under
• Updated
• Added a note in
• Updated Asymmetric Mode Min, Symmetric Mode Min, and Max columns of
• Removed Conditions parameters of the Full scale output voltage row in
• Updated
• In
• In
• In
• Added a new section
• In
• In
• In
• Updated Signal and Direction columns in
• Updated Signal names in
• Updated the Minimum and Maximum columns in
(AN4053)i.MX51”.
Characteristics," on page 27
"DDR2 I/O Output Buffer Impedance HVE = 0," on page
Electrical Characteristics for DDR2”.
(for square wave input) parameter, the minimum frequency was changed to NVCC_PER3
- 0.25V and the maximum frequency was changed to NVCC_PER3.
with ATA/ATAPI-5 specification.
Synchronous Internal Clock Operation sections for the ID SS42, minimum frequency was
changed from 10.0 to 30.
Clock Operation section for ID SS20, minimum frequency was changed from 10.0 to 30.
Clock Operation section for ID SS38, maximum frequency was changed from 15.0 to 30.
for IDs SS28 and SS29, direction was changed from out to in.
IDs US40 and US41, direction was changed from out to in and the reference signal was
changed to USB_VM1 and USB_VP1 respectively.
extra row for for ID17.
Unidirectional Mode," on page
Bi-directional Mode," on page
"Ordering Information," on page
page
Table 104, "SSI Transmitter Timing with External Clock," on page
Table 118, "USB Port Timing Specification in VP_VM Bi-directional Mode," on page
Table 102, "SSI Transmitter Timing with Internal Clock," on page
Table 103, "SSI Receiver Timing with Internal Clock," on page
Table 120, "USB Timing Specification in VP_VM Unidirectional Mode," on page
Table 122, "USB Timing Specification for ULPI Parallel Mode," on page
19.
Section 3, “IOMUX Configuration for Boot
Table 47, "CAMP Electrical Parameters (CKIH1, CKIH2)," on page
Section 4.7.11, “P-ATA Timing
Figure 2, "Power-Up Sequence," on page
Section , “For more information on power up, see i.MX51 Power-Up Sequence
Section 4.2.1, “Power-Up
Section 4.6.6, “NAND Flash Controller (NFC)
Section 4.7.16.1, “UART
Table 118, "USB Port Timing Specification in VP_VM
Section 4.5, “I/O AC
to Input current (75 kO Pull-up).
145.Updated CaseTemperature Range column in
147.
Substantive Change(s)
3.
Table 3, "Special Signal Considerations," on page
Parameters”. Replaced ATA/ATAPI-6 specification
Table 120, "USB Timing Specification in VP_VM
Sequence”.
Electrical”, under
Parameters”. See
Table 13, "i.MX51 Operating Ranges," on
Media”.
24.
Table 21, "UHVIO DC Electrical
31.
Parameters” after
Section 4.7.16,
133, under the Internal
Section 4.5.4, “AC
135, under the External
Freescale Semiconductor
132, under the
Table
148, added an
47. In the VIH
Table
82.
Table 1,
Table 27,
“UART”.
Table
147, for
50.
145,
12.
49.