MCIMX515DJM8C Freescale, MCIMX515DJM8C Datasheet - Page 6

• Manufacturer Part Number: MCIMX515DJM8C
• Manufacturer: Freescale

Specifications of MCIMX515DJM8C

• Operating Temperature (min): -20C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Features
6
Mnemonic
eSDHC-1
eSDHC-2
eSDHC-3
EPIT-1
EPIT-2
Block
EMI
External
Memory
Interface
Enhanced
Periodic
Interrupt
Timer
Enhanced
Multi-Media
Card/
Secure Digital
Host
Controller
Block Name
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4
Table 2. i.MX51 Digital and Analog Modules (continued)
Connectivity
Peripherals
Timer
Peripherals
Connectivity
Peripherals
Subsystem
The EMI is an external and internal memory interface. It performs arbitration
between multi-AXI masters to multi-memory controllers, divided into four major
channels: fast memories (Mobile DDR, DDR2) channel, slow memories
(NOR-FLASH/PSRAM/NAND-FLASH and so on) channel, internal memory
(RAM, ROM) channel and graphical memory (GMEM) Channel.
In order to increase the bandwidth performance, the EMI separates the buffering
and the arbitration between different channels so parallel accesses can occur.
By separating the channels, slow accesses do not interfere with fast accesses.
EMI features:
Each EPIT is a 32-bit “set and forget” timer that starts counting after the EPIT is
enabled by software. It is capable of providing precise interrupts at regular
intervals with minimal processor intervention. It has a 12-bit prescaler for division
of input clock frequency to get the required time setting for the interrupts to occur,
and counter values can be programmed on the fly.
The features of the eSDHC module, when serving as host, include the following:
• 64-bit and 32-bit AXI ports
• Enhanced arbitration scheme for fast channel, including dynamic master
• Flexible bank interleaving
• Supports 16/32-bit Mobile DDR up to 200 MHz SDCLK (mDDR400)
• Supports 16/32-bit (Non-Mobile) DDR2 up to 200 MHz SDCLK (DDR2-400)
• Supports up to 2 Gbit Mobile DDR memories
• Supports 16-bit (in muxed mode only) PSRAM memories (sync and async
• Supports 32-bit NOR-Flash memories (only in muxed mode), at slow
• Supports 4/8-ECC, page sizes of 512 Bytes, 2 Kbytes and 4 Kbytes
• NAND-Flash (including MLC)
• Multiple chip selects
• Enhanced Mobile DDR memory controller, supporting access latency hiding
• Supports watermarking for security (Internal and external memories)
• Supports Samsung OneNAND
• Conforms to SD Host Controller Standard Specification version 2.0
• Compatible with the MMC System Specification version 4.2
• Compatible with the SD Memory Card Specification version 2.0
• Compatible with the SDIO Card Specification version 1.2
• Designed to work with SD Memory, miniSD Memory, SDIO, miniSDIO, SD
• Configurable to work in one of the following modes:
• Full-/high-speed mode
• Host clock frequency variable between 32 kHz to 52 MHz
• Up to 200 Mbps data transfer for SD/SDIO cards using four parallel data lines
• Up to 416 Mbps data transfer for MMC cards using eight parallel data lines
priority, and taking into account which pages are open or closed and what type
(Read or Write) was the last access
operating modes), at slow frequency, for debugging purposes
frequencies for debugging purposes
Combo, MMC and MMC RS cards
—SD/SDIO 1-bit, 4-bit
—MMC 1-bit, 4-bit, 8-bit
Brief Description
™
(only in muxed I/O mode)
Freescale Semiconductor