AD9515BCPZ Analog Devices Inc, AD9515BCPZ Datasheet
AD9515BCPZ
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AD9515BCPZ Summary of contents
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FEATURES 1.6 GHz differential clock input 2 programmable dividers Divide-by in range from1 to 32 Phase select for coarse delay adjust 1.6 GHz LVPECL clock output Additive output jitter 225 fs rms 800 MHz/250 MHz LVDS/CMOS clock output Additive output ...
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AD9515 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Clock Input.................................................................................... 3 Clock Outputs ............................................................................... 3 Timing Characteristics ................................................................ 4 Clock Output Phase Noise .......................................................... ...
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SPECIFICATIONS Typical (typ) is given for V = 3.3 V ± 5 and maximum (max) values are given over full V CLOCK INPUT Table 1. Parameter CLOCK INPUT (CLK) Input Frequency 1 1 Input Sensitivity Input Common-Mode Voltage, ...
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AD9515 TIMING CHARACTERISTICS CLK input slew rate = 1 V/ns or greater. Table 3. Parameter LVPECL Output Rise Time Output Fall Time PROPAGATION DELAY CLK-TO-LVPECL OUT PECL Divide = 1 Divide = 2 − ...
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Parameter Zero Scale Delay Time Zero Scale Variation with Temperature 2 Full Scale Time Delay Full Scale Variation with Temperature Linearity, DNL Linearity, INL 1 This is the difference between any two similar delay paths across ...
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AD9515 Parameter CLK = 491.52 MHz, OUT = 245.76 MHz Divide = Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset CLK = 245.76 MHz, ...
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Parameter CLK = 491.52 MHz, OUT = 122.88 MHz Divide = Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK ...
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AD9515 Parameter CLK = 78.6432 MHz, OUT = 78.6432 MHz Divide = Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset ...
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Parameter CMOS OUTPUT ADDITIVE TIME JITTER CLK = 400 MHz CMOS (OUT1) = 100 MHz Divide = 4 CLK = 400 MHz CMOS (OUT1) = 100 MHz Divide = 4 LVPECL (OUT0 MHz 1 DELAY BLOCK ADDITIVE TIME ...
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AD9515 POWER Table 7. Parameter 1 POWER-ON SYNCHRONIZATION V Transit Time from 2 3 POWER DISSIPATION POWER DELTA Divider (Divide = 2 to Divide = 1) LVPECL Output LVDS Output CMOS Output (Static) CMOS Output (@ ...
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TIMING DIAGRAMS t CLK CLK t PECL t LVDS t CMOS Figure 2. CLK/CLKB to Clock Output Timing, Divide = 1 Mode DIFFERENTIAL 80% LVPECL 20 Figure 3. LVPECL Timing, Differential DIFFERENTIAL 20% SINGLE-ENDED 20 Rev. ...
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AD9515 ABSOLUTE MAXIMUM RATINGS Table 8. With Respect to Parameter or Pin VS GND RSET GND CLK, CLKB GND CLK CLKB OUT0, OUT0B, OUT1, OUT1B GND 1 Junction Temperature Storage Temperature Lead Temperature (10 sec) ESD CAUTION ESD (electrostatic discharge) ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VS 1 CLK 2 CLKB 3 AD9515 VS 4 TOP VIEW (Not to Scale) SYNCB 5 VREF 6 S10 Figure 6. 32-Lead LFCSP Pin Configuration Note that the exposed paddle on this ...
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AD9515 TERMINOLOGY Phase Jitter and Phase Noise An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0 to 360 degrees for each cycle. Actual signals, however, display a certain ...
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TYPICAL PERFORMANCE CHARACTERISTICS 0.3 LVPECL (DIV ON) 0.2 LVDS (DIV ON) 0.1 400 800 OUTPUT FREQUENCY (MHz) Figure 8. Power vs. Frequency—LVPECL, LVDS START 300kHz STOP 5GHz Figure 9. CLK Smith Chart (Evaluation Board) 0.5 0.4 LVPECL (DIV = 1) ...
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AD9515 VERT 500mV/DIV Figure 11. LVPECL Differential Output @ 1600 MHz VERT 100mV/DIV Figure 12. LVDS Differential Output @ 800 MHz VERT 500mV/DIV Figure 13. CMOS Single-Ended Output @ 250 MHz with 10 pF Load 1.8 1.7 1.6 1.5 1.4 ...
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OFFSET (Hz) Figure 17. Additive Phase Noise—LVPECL, Divide = 1, 245.76 MHz –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 10 100 1k 10k 100k OFFSET ...
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AD9515 FUNCTIONAL DESCRIPTION OVERALL The AD9515 provides for the distribution of its input clock on one or both of its outputs. OUT0 is an LVPECL output. OUT1 can be set to either LVDS or CMOS logic levels. Each output has ...
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Synchronization is initiated by pulling the SYNCB pin low for a minimum of 5 ns. The input clock does not have to be present at the time the command is issued. The synchronization occurs after four input clock cycles. The ...
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AD9515 PROGRAMMING Table 10. S0—OUT1 Delay Full Scale S0 Delay 0 Bypassed 1/3 1 Table 11. S1—Output Logic Configuration S1 OUT0 OUT1 0 LVPECL 790 mV LVDS 1/3 LVPECL 400 mV LVDS 2/3 ...
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Table 13. S5, S6, and S7—OUT1 OUT1 Divide (Duty Cycle 1 (50%) 2 (33 (50 (40%) 1/3 1/3 0 ...
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AD9515 DIVIDER PHASE OFFSET The phase offset of OUT0 and OUT1 can be selected (see Table 12 to Table 15). This allows the relative phase of OUT0 and OUT1 to be set. After a SYNC operation (see the Synchronization section), ...
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When the delay block is OFF (bypassed also powered down. OUTPUTS The AD9515 offers three different output level choices: LVPECL, LVDS, and CMOS. OUT0/OUT0B offers an LVPECL differential output. The LVPECL differential voltage swing (V ) can be ...
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AD9515 Exposed Metal Paddle The exposed metal paddle on the AD9515 package is an electrical connection, as well as a thermal enhancement. For the device to function properly, the paddle must be properly attached to ground (GND). The exposed paddle ...
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APPLICATIONS USING THE AD9515 OUTPUTS FOR ADC CLOCK APPLICATIONS Any high speed, analog-to-digital converter (ADC) is extremely sensitive to the quality of the sampling clock provided by the user. An ADC can be thought sampling mixer, and ...
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AD9515 LVDS CLOCK DISTRIBUTION The AD9515 provides one clock output (OUT2) that is selectable as either CMOS or LVDS levels. Low voltage differential signaling ( LVDS differential output option for OUT2. LVDS uses a current mode output stage. ...
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PHASE NOISE AND JITTER MEASUREMENT SETUPS WENZEL EVALUATION BOARD OSCILLATOR SPLITTER 0° ZESC-2-11 EVALUATION BOARD WENZEL OSCILLATOR ⎡ V ⎢ A_RMS ⎢ ⎣ J_RMS where the rms time jitter. j_RMS SNR is the signal-to-noise ratio. ...
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... PLANE ORDERING GUIDE Model Temperature Range AD9515BCPZ 1 −40°C to +85°C 1 AD9515BCPZ-REEL7 −40°C to +85°C AD9515/PCB Pb-free part. © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05597–0–7/05(0) 5.00 ...