AD9515BCPZ Analog Devices Inc, AD9515BCPZ Datasheet - Page 10

• Manufacturer Part Number: AD9515BCPZ
• Description: IC CLOCK DIST 2OUT PLL 32LFCSP
• Manufacturer: Analog Devices Inc
• Type: Fanout Buffer (Distribution), Dividerr

Specifications of AD9515BCPZ

• Design Resources: Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109)
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: Yes/Yes
• Input: Differential
• Output: CMOS, LVDS, LVPECL
• Frequency - Max: 1.6GHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Frequency-max: 1.6GHz
• No. Of Multipliers / Dividers: 2
• No. Of Amplifiers: 3
• Supply Voltage Range: 3.135V To 3.465V
• Slew Rate: 1V/ns
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9515/PCBZ - BOARD EVAL CLOCK 2CH AD9515
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9515
POWER
Table 7.
Parameter
POWER-ON SYNCHRONIZATION
POWER DISSIPATION
POWER DELTA
1
This is the rise time of the V
transition the range from 2.2 V to 3 .1 V. If the rise time is too slow, the outputs will not be synchronized.
V
Divider (Divide = 2 to Divide = 1)
LVPECL Output
LVDS Output
CMOS Output (Static)
CMOS Output (@ 62.5 MHz)
CMOS Output (@ 125 MHz)
Delay Block
S
Transit Time from 2.2 V to 3.1 V
S
supply that is required to ensure that a synchronization of the outputs occurs on power-up. The critical factor is the time it takes the V
1
Min
215
300
330
110
15
65
20
30
80
30
Typ
285
370
405
110
150
30
90
50
40
45
Max
380
465
510
125
140
190
35
45
85
50
65
Rev. 0 | Page 10 of 28
Unit
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
ms
Test Conditions/Comments
See the Power-On SYNC section.
Both outputs on. LVPECL (divide = 2), LVDS (divide = 2). No clock.
Does not include power dissipated in external resistors.
Both outputs on. LVPECL (divide = 2), CMOS (divide = 2);
at 62.5 MHz out (5 pF load).
Both outputs on. LVPECL, CMOS (divide = 2);
at 125 MHz out (5 pF load).
For each divider. No clock.
For each output. No clock.
No clock.
No clock.
Single-ended. At 62.5 MHz out with 5 pF load.
Single-ended. At 125 MHz out with 5 pF load.
Off to 1.5 ns fs, delay word = 60; output clocking at 62.5 MHz.
S
to