AD9515BCPZ Analog Devices Inc, AD9515BCPZ Datasheet - Page 13

• Manufacturer Part Number: AD9515BCPZ
• Description: IC CLOCK DIST 2OUT PLL 32LFCSP
• Manufacturer: Analog Devices Inc
• Type: Fanout Buffer (Distribution), Dividerr

Specifications of AD9515BCPZ

• Design Resources: Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109)
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: Yes/Yes
• Input: Differential
• Output: CMOS, LVDS, LVPECL
• Frequency - Max: 1.6GHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Frequency-max: 1.6GHz
• No. Of Multipliers / Dividers: 2
• No. Of Amplifiers: 3
• Supply Voltage Range: 3.135V To 3.465V
• Slew Rate: 1V/ns
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9515/PCBZ - BOARD EVAL CLOCK 2CH AD9515
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Note that the exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to
function properly, the paddle must be soldered to a PCB land that functions as both a heat dissipation path as well as an electrical
ground (analog).
Table 9. Pin Function Descriptions
Pin No.
1, 4, 17, 20, 21, 24, 26, 29, 30
2
3
5
6
7 to 16, 25
18
19
22
23
27, 28
31, Exposed Paddle
32
SYNCB
CLKB
VREF
CLK
S10
VS
VS
S9
1
2
4
5
6
7
8
3
Figure 6. 32-Lead LFCSP Pin Configuration
(Not to Scale)
AD9515
TOP VIEW
CLK
CLKB
SYNCB
VREF
S0 to S10
OUT1B
OUT1
OUT0B
OUT0
DNC
RSET
Mnemonic
VS
GND
Description
Power Supply (3.3 V).
Clock Input.
Complementary Clock Input. Used in conjunction with CLK.
Used to Synchronize the Outputs; Active Low Signal.
Provides 2/3 V
Programming Pins. These pins determine the operation of the AD9515; 4-state logic.
Complementary LVDS/Inverted CMOS Output. Includes a delay block.
LVDS/CMOS Output. Includes a delay block.
Complementary LVPECL Output.
LVPECL Output.
Do Not Connect.
Ground. The exposed paddle on the back of the chip is also GND.
Current Sets Resistor to Ground. Nominal value = 4.12 kΩ.
24 VS
23 OUT0
22 OUT0B
21 VS
20 VS
19 OUT1
18 OUT1B
17 VS
Rev. 0 | Page 13 of 28
S
Reference Voltage for Use with Programming Pins S0 to S10.
24
17
16
THERMAL CONNECTION
IS AN ELECTRICAL AND
25
THE EXPOSED PADDLE
Figure 7. Exposed Paddle
(BOTTOM VIEW)
EXPOSED PAD
GND
32
9
1
8
AD9515