AD9515BCPZ Analog Devices Inc, AD9515BCPZ Datasheet - Page 25

• Manufacturer Part Number: AD9515BCPZ
• Description: IC CLOCK DIST 2OUT PLL 32LFCSP
• Manufacturer: Analog Devices Inc
• Type: Fanout Buffer (Distribution), Dividerr

Specifications of AD9515BCPZ

• Design Resources: Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109)
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: Yes/Yes
• Input: Differential
• Output: CMOS, LVDS, LVPECL
• Frequency - Max: 1.6GHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Frequency-max: 1.6GHz
• No. Of Multipliers / Dividers: 2
• No. Of Amplifiers: 3
• Supply Voltage Range: 3.135V To 3.465V
• Slew Rate: 1V/ns
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9515/PCBZ - BOARD EVAL CLOCK 2CH AD9515
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

APPLICATIONS
USING THE AD9515 OUTPUTS FOR ADC CLOCK
APPLICATIONS
Any high speed, analog-to-digital converter (ADC) is extremely
sensitive to the quality of the sampling clock provided by the
user. An ADC can be thought of as a sampling mixer, and any
noise, distortion, or timing jitter on the clock is combined with
the desired signal at the A/D output. Clock integrity require-
ments scale with the analog input frequency and resolution,
with higher analog input frequency applications at ≥14-bit
resolution being the most stringent. The theoretical SNR of an
ADC is limited by the ADC resolution and the jitter on the
sampling clock. Considering an ideal ADC of infinite resolution
where the step size and quantization error can be ignored, the
available SNR can be expressed approximately by
where f is the highest analog frequency being digitized.
t
Figure 35 shows the required sampling clock jitter as a function
of the analog frequency and effective number of bits (ENOB).
See Application Notes AN-756 and AN-501 at www.analog.com.
j
is the rms jitter on the sampling clock.
110
100
90
80
70
60
50
40
30
SNR
10
f
A
Figure 35. ENOB and SNR vs. Analog Input Frequency
=
FULL-SCALE SINE WAVE ANALOG FREQUENCY (MHz)
20
×
log
⎡
⎢
⎣
2π
1
ft
J
⎤
⎥
⎦
100
SNR = 20log
2πf
1
A
T
J
1k
18
16
14
12
10
8
6
Rev. 0 | Page 25 of 28
Many high performance ADCs feature differential clock inputs
to simplify the task of providing the required low jitter clock on
a noisy PCB. (Distributing a single-ended clock on a noisy PCB
can result in coupled noise on the sample clock. Differential
distribution has inherent common-mode rejection that can
provide superior clock performance in a noisy environment.)
The AD9515 features both LVPECL and LVDS outputs that
provide differential clock outputs, which enable clock solutions
that maximize converter SNR performance. The input
requirements of the ADC (differential or single-ended, logic
level, termination) should be considered when selecting the best
clocking/converter solution.
LVPECL CLOCK DISTRIBUTION
The low voltage, positive emitter-coupled, logic (LVPECL)
outputs of the AD9515 provide the lowest jitter clock signals
available from the AD9515. The LVPECL outputs (because they
are open emitter) require a dc termination to bias the output
transistors. The simplified equivalent circuit in Figure 31 shows
the LVPECL output stage.
In most applications, a standard LVPECL far-end termination is
recommended, as shown in Figure 36. The resistor network is
designed to match the transmission line impedance (50 Ω) and
the switching threshold (V
LVPECL
V
LVPECL
S
V
S
200Ω
Figure 37. LVPECL with Parallel Transmission Line
Figure 36. LVPECL Far-End Termination
V
(NOT COUPLED)
SINGLE-ENDED
0.1nF
0.1nF
T
200Ω
= V
S
100Ω DIFFERENTIAL
50Ω
50Ω
– 1.3V
S
(COUPLED)
− 1.3 V).
127Ω
83Ω
V
S
100Ω
127Ω
83Ω
LVPECL
V
LVPECL
AD9515
S
V
S