S19252PBIDB Applied Micro Circuits Corporation, S19252PBIDB Datasheet
S19252PBIDB
Specifications of S19252PBIDB
Related parts for S19252PBIDB
S19252PBIDB Summary of contents
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STS-192 SONET/SDH/FEC/GbE/FC 16-bit Transceiver with EDC General Features • Operational from 9.9 Gbps to 11.32 Gbps • Built-In Self Test (BIST) with Error Counter • On-chip High-Frequency PLLs for Clock Recovery and Clock Generation • 16-bit LVDS Parallel Data Path ...
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S19252 Data Sheet NOTICE: THIS IS A “RELEASED” SPECIFICATION This document is a RELEASED specification for a device under development by AppliedMicro: • Specifications in this document are not guaranteed to be the latest and are subject to change. • ...
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GENERAL FEATURES ........................................................................................................................................... 1 Transmitter Features ......................................................................................................................................... 1 Receiver Features ............................................................................................................................................. 1 APPLICATIONS ...................................................................................................................................................... 1 GENERAL DESCRIPTION ...................................................................................................................................... 1 DATA SHEET TYPE ................................................................................................................................................ 2 TABLE OF CONTENTS .......................................................................................................................................... 3 LIST OF FIGURES .................................................................................................................................................. 6 LIST OF TABLES .................................................................................................................................................... 7 S19252 ...
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S19252 Data Sheet SERDATIP/N Internal Termination (CENTER_TAP) – External Pin ............................................................... 15 Receive Loop Filter (RXCAP1, RXCAP2) – External Pin ................................................................................ 15 Receiver Reset (RX_RSTB) – Register ........................................................................................................... 15 Lock-to-Reference (LCKREFN) – Register ..................................................................................................... 16 LOS/Signal Detect (LOS_SD) – External ...
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Clock Synthesizer ............................................................................................................................................ 25 Loop Timing ..................................................................................................................................................... 25 Line Loopback ................................................................................................................................................. 25 Timing Generator ............................................................................................................................................. 25 FIFO ................................................................................................................................................................ 26 FIFO Initialization ............................................................................................................................................. 26 Parallel-to-Serial Converter ............................................................................................................................. 26 Duo-Binary Encoding ....................................................................................................................................... 26 Transmit Built-In Self Test Mode ..................................................................................................................... 26 RECEIVER FUNCTIONAL ...
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S19252 Data Sheet Figure 1: System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 1: Transmit Reference Source Select ...
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S19252 Data Sheet S19252 Overview The S19252 transceiver incorporates SONET/SDH/10 GbE/10 G Fibre Channel serialization deserialization functions. This chip can be used to implement the front end of SONET/10 GbE/10 G Fibre Channel equipment, which consists primarily of the serial ...
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Figure 5: Transceiver Functional Block Diagram Normal Font – External Pin Access Only Italics Font – Serial Bus Register Access Only Italics and Bold Font – External Pin And Serial Bus Register Access Revision 5.03 AppliedMicro - Confidential and Proprietary ...
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S19252 Data Sheet Transmit Input Pin Description Parallel Input Data (PINP/N[15:0]) – External Pin PINP/N[15:0] is the LVDS parallel data input bus which is multiplexed 16:1 and transmitted serially at STS-192/ 10 GbE/10G FC rates. This data is aligned with ...
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CSU Ref. Clock (REFCLKAP/N) – External Pin The differential CML Reference Clock (REFCLKAP/N by default) input is used to drive the clock synthesizer Phase Lock Loop (PLL). See Table 3, Reference Frequency (CSU REFCLK) for the Clock Synthesis Unit and ...
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S19252 Data Sheet Table 3: Reference Frequency (CSU REFCLK) for the Clock Synthesis Unit SONET_ GBE_ TXREF RATE RATE SEL SEL SEL Gigabit Ethernet ...
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Clock Synthesizer Input (CSU_INP/N) – External Pin The clock synthesizer input is the differential REFCLK CML input to the internal CSU. This input is typically driven from an external VCO, which is controlled by an external loop filter and the ...
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S19252 Data Sheet Automatic FIFO Initialization (AUTO_FIFO_INIT) – Register This active high control input internally connects the transmit FIFO signals (PHERR output and PHINIT input) and automatically initializes the FIFO in case of a PCLK/PICLK set-up or hold time violation. ...
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Phase Error (PHERR) – Register Phase Error is an active high output. To prevent errors caused by short set-up or hold times between the PICLK and internally generated PCLK, the timing generator circuitry monitors the phase relationship between the two ...
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S19252 Data Sheet Lock-to-Reference (LCKREFN) – Register The active low Lock-to-Reference (LCKREFN) input register, when asserted low, will force the PLL to lock to the Reference Clock defined by the RXREFSEL and de-assert RX_LOCKDET. The POCLKP/N will lock to the ...
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CRU Reference Clock (REFCLKAP/N) – External Pin The differential REFCLK CML equivalent FEC/10 Gigabit Ethernet Rate) reference clock (CRU REFCLKP/N) input is used to establish the initial operating frequency of the Phase Lock Loop (PLL). This input can also be ...
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S19252 Data Sheet Kill Parallel Output Clock (KILLPOCLK) – Register The active high Kill Parallel Output Clock (KILLPOCLK) signal, when asserted high, will force the POCLK output to a state specified by the CLKSTOP_VAL register bit. This input may be ...
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Table 8: Phase Adjust Control Phase Adjust Input (PHASE_ADJ Phase Adjustment The BOLD ...
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S19252 Data Sheet Parallel Output Data Bus Swap (RX_DATA_SWAP) – Register This input reverses the order of the parallel output data bus (POUTP/N[15:0]). This makes routing easier with configurations requiring Data Bus bit order reversal. AppliedMicro recommends that DATA_SWAP input ...
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Common Input Pin Description Reset (RSTB) – External Pin This active low LVCMOS Reset (RSTB) input asynchronously resets the device. All clocks, including PCLK, are disabled during reset. For normal system operation, V should be connected to RSTB input. DD_3.3V ...
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S19252 Data Sheet In the RLPTIME mode, the internal POCLK is fed into the phase detector block. The output of the phase detector block is fed into the external VCO. The output of the external VCO then goes into the ...
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User Defined BIST Pattern (BIST_PTRN[15:0]) – Register This is a user defined pattern which is output from the transmit or the receive pattern generator. This pattern is loaded on the rising edge of TX_BIST_EN or RX_BIST_EN. The user defined pattern ...
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S19252 Data Sheet Common Output Pin Description Transmit and Receive Alarm (TX_RX_ALARM) – Register and External Pin The active high LVCMOS transmit and receive alarm (TX_RX_ALARM) signal indicates an active alarm on the transmit or the receive output. This output ...
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Clock Synthesizer The clock synthesizer shown in the block diagram in Figure monolithic PLL that generates the serial output clock frequency locked to the input Reference Clock (CSU_REFCLKP/N). The CSU_REFCLKP/N input must be generated from a crystal ...
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S19252 Data Sheet FIFO A FIFO is added to decouple the internal and external parallel clocks. The internally generated divide-by-16 clock (PCLK) is used to clock out data from the FIFO. PHINIT and TX_LOCKDET are used to center or reset ...
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The user defined pattern can be loaded through the BIST_PTRN[15:0] register. There are two modes of transmit BIST operation: 1. Normal operation with DLEB disabled 2. Normal operation with DLEB enabled When the diagnostic loopback mode is not active, the ...
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S19252 Data Sheet The frequency detector ensures predictable lock conditions used during acquisition and serves as a means to pull the VCO into the range of the data rate where the phase detector is capable of acquiring lock. ...
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Receive Built-In Self Test Mode The S19252 circuitry includes a PRBS generator and a checker. The receive built-in self test allows for the verification of the parallel input and output data paths in the S19252. The S19252 goes in the ...
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S19252 Data Sheet Input/Output Controls Mode Control S19252 has external mode control pins that offers users device IO configuration selections. Mode control is accomplished by external pins. The following are the features of mode control as shown in Table 15: ...
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Serial Interface Mode The S19252 has multiple serial interface modes that support MDIO, I2C and SPI interfaces. See Table 16. Table 16: Serial Interface Mode Pull Pull Pull Down Down Down ADDRE Pull Pull Down ...
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S19252 Data Sheet MDIO Bus and Address Register S19252 uses (as Default) a simple bi-directional two- wire bus for efficient inter-IC control. This bus reads from and writes into most of the S19252 control logic. The following are some important ...
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Table 17: Serial Port Frame Format START OF OPERATION FRAME CODE Read 01 10 Write 01 01 Read Frame Sequence While Changing Page Address[XXX] Write 01 01 Read 01 10 Write Frame Sequence While Changing Page Address[XXX] Write 01 01 ...
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S19252 Data Sheet 2 ® BUS and Address Register S19252 has the option to use a simple I directional two-wire bus for efficient inter-IC control. All register controlled features and 2 ® programmed via the I C BUS ...
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Serial Peripheral Interface (SPI) S19252 has the option to use a simple SPI bi- directional serial bus for efficient inter-IC control. All register controlled features and programmed via the SPI bus. A detailed register map description can found in the ...
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S19252 Data Sheet SONET and Ethernet Jitter Criteria SONET Jitter Transfer The following jitter transfer requirement applies to STS- 192 interfaces as defined in GR-253-CORE. For STS- 192 interfaces, the jitter transfer function shall be under the curve in Figure ...
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SONET Jitter Generation The following jitter generation requirement applies to STS-192 interfaces as defined in GR-253-CORE. According to GR-253-CORE, jitter generation shall not exceed 0.10 UI for STS-192 interfaces when PP measured using a bandpass measurement filter with a high-pass ...
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S19252 Data Sheet Sinusoidal Jitter The Sj applied for tolerance testing is defined by the jitter mask shown in Figure 10 and Table 18 (per IEEE 802.3ae). The Loop Bandwidth (LB) for S19252 is approximately 8 MHz. Test Pattern Test ...
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Figure 10: Applied Sinusoidal Jitter - 10 GbE 5 UI Applied Sinusoidal Jitter peak-to-peak Amplitude (UI) (Log Scale) 0.05 UI Table 18: Applied Sinusoidal Jitter Frequency Range f < 40 kHz 40 kHz < f < 4 MHz 4 MHz ...
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S19252 Data Sheet Table 19: Pattern Segments Segments Table 20: Test Patterns Pattern AppliedMicro - Confidential and Proprietary Seed [57:0] 0x3C8B44DCAB6804F 0x34906BB85A38884 Inverted Seed for A n Inverted Seed ...
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Register Map Table 21 below contains the register map summary for the S19252 device. When programming the S19252 device, care should be taken to preserve the default state of all RESERVED register bits. Consult the Programmer’s Reference Manual, PRM2010, for ...
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S19252 Data Sheet Table 21: Register Map Summary (Continued) Reset A Addr. Value Bit 7 Bit 6 Reserved Reserved 0x11-15 - N/A N/A 0x16 xxxx xxxx Reserved Reserved 0x17 - N/A N/A Reserved Reserved 0x18 xxxx 1000 N/A N/A 0x19 ...
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Table 21: Register Map Summary (Continued) Reset A Addr. Value Bit 7 Bit 6 Reserved Reserved 0x34 0010 1010 N/A N/A Reserved Reserved 0x35-3F - N/A N/A MDIO_PAGE[2] MDIO_PAGE[1] B 0x40 0000 0000 RW RW Reserved Reserved 0x41 - - ...
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S19252 Data Sheet Table 21: Register Map Summary (Continued) Reset A Addr. Value Bit 7 Bit 6 PRBS_RXCHK_ PRBS_RXGEN_ INV INV 0x89 0011 000x RW RW Reserved Reserved 0x8A-91 - N/A N/A Reserved Reserved 0x92 1000 1111 N/A N/A Reserved ...
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Pin Assignments and Descriptions Table 22: Input Pin Assignments and Descriptions Pin Name Level TX_DATA TX_DATA SWAP = 0 SWAP = 1 PINP0 PINP15 LVDS PINN0 PINN15 PINP1 PINP14 PINN1 PINN14 PINP2 PINP13 PINN2 PINN13 PINP3 PINP12 PINN3 PINN12 PINP4 ...
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S19252 Data Sheet Table 22: Input Pin Assignments and Descriptions (Continued) Pin Name Level TXCAP1 Analog TXCAP2 XVCO Register 0x01h XVCO155 Register 0x01h REFSEL Register 0x79h PHINIT Register 0x03h AUTO_FIFO_INIT Register 0x03h KILLPCLK Register 0x01h KILLTXMCK Register 0x01h TX_BIST_EN Register ...
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Table 22: Input Pin Assignments and Descriptions (Continued) Pin Name Level TAP[2:0]_CNTL Register 0x0B-0Ch CSU_INP REFCLK CSU_INN Diff CML TXPD LVCMOS Pull Down TX_DATA_SWAP Register 0x0Bh LVDS_INPUT_AC_EN Register 0x03h SERDATIP High SERDATIN Speed Diff CML CENTER_TAP Analog PAOFFADJ9 Register PAOFFADJ8 ...
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S19252 Data Sheet Table 22: Input Pin Assignments and Descriptions (Continued) Pin Name Level PAEQ_LINKOPT14 Register PAEQ_LINKOPT13 0x1E-1Fh PAEQ_LINKOPT12 PAEQ_LINKOPT11 PAEQ_LINKOPT10 PAEQ_LINKOPT24 Register PAEQ_LINKOPT23 0x1Ch PAEQ_LINKOPT22 PAEQ_LINKOPT21 PAEQ_LINKOPT20 PHASE_ADJ2 Register PHASE_ADJ1 0x7Fh PHASE_ADJ0 REFCLKBP REFCLK REFCLKBN Diff CML RXCAP1 Analog ...
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Table 22: Input Pin Assignments and Descriptions (Continued) Pin Name Level KILLRXMCK Register 0x01h KILLPOCLK Register 0x01h RX_BIST_EN Register 0x85h RX_BIST_CLR Register 0x85h RXPD LVCMOS Pull Down RX_DATA_SWAP Register 0x0Bh RSTB LVCMOS Pull Up DLEB Register 0x01h LLEB Register 0x02h ...
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S19252 Data Sheet Table 22: Input Pin Assignments and Descriptions (Continued) Pin Name Level RLPTIME Register 0x03h CLKSTOP_VAL Register 0x05h BIST_PTRN[15:0] Register 0x87-88h PRBS_SELECT[1:0] Register 0x89h BER_SELECT[2:0] Register 0x83h BER_RSTB Register 0x86h 50 AppliedMicro - Confidential and Proprietary I/O Pin# ...
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Table 23: Output Pin Assignments and Descriptions Pin Name Level TSDP High TSDN Speed diff CML TSCLKP High TSCLKN Speed diff CML PCLKP LVDS PCLKN TX_155MCKP LVDS TX_155MCKN TX_LOCKDET LV CMOS & Regis- ter Pull Up PHERR Register 0x82h PD_UPP ...
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S19252 Data Sheet Table 23: Output Pin Assignments and Descriptions (Continued) Pin Name Level POCLKP LVDS POCLKN RX_DATA RX_DATA SWAP = 0 SWAP = 1 POUTP0 POUTP15 LVDS POUTN0 POUTN15 POUTP1 POUTP14 POUTN1 POUTN14 POUTP2 POUTP13 POUTN2 POUTN13 POUTP3 POUTP12 ...
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Table 23: Output Pin Assignments and Descriptions (Continued) Pin Name Level RX_BIST_ERR Register 0X85h TX_RX_ALARM LV CMOS & Regis- ter Pull Up BIST_ACTIVE Register 0x85h BER_COUNT[11:0] Register 0x84-85h BER_OVERFLOW Register 0x83h TERM_COUNT Register 0X89H Table 24: S19252 JTAG Pin Assignments ...
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S19252 Data Sheet Table 25: S19252 MPIO Pin Assignments and Descriptions 1 Pin Name Level Register MDIO/I2C Control Device Interface Addressing Pins Pins MPIO_7 I2C (SDA) MPIO_6 I2C (SCL) ADDRESS4 & LV CMOS Pull down MPIO_5 LV (MDIO) CMOS (SPI/SDI) ...
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Table 25: S19252 MPIO Pin Assignments and Descriptions (Continued) 1 Pin Name Level SCAN- LV MODE CMOS Pull down 1. See Table 16 for termination of serial interface configuration. Table 26: Power and Ground Pin Assignments and Descriptions Pin Name ...
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S19252 Data Sheet S19252 – 324 PBGA Pinout - 0.8 mm Pitch (Bottom View) Data_swap = 0 Figure 12: S19252 – 324 PBGA Pinout - 0.8 mm Pitch (Bottom View) Data_swap = ...
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S19252 – 324 PBGA 0.8 mm Pitch Package Mechanical Drawing Figure 13: S19252 – 324 PBGA 0.8 mm Pitch Package Mechanical Drawing PACKAGE MATERIAL NOTE: Standard Package: Ball Composition - 63/37 Sn/Pb. RoHS Compliant Package: Ball Composition - 96.5/3.0/0.5 Sn/Ag/Cu. ...
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S19252 Data Sheet S19252 – 324 PBGA Package Marking Drawing Figure 14: S19252 – 324 PBGA Package Marking Drawing (Top View) NOTES (Unless Otherwise Specified ): Dot Represents PIN1 (A01) Designator 1 ES (Engineering Sample) designator. When present, this signifies ...
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Performance Specifications Table 28: Performance Specifications Parameter Nominal VCO Center Frequency (CSU and CRU) TX and RX VCO frequency ([T/R]X_VCO_Range = 00) TX and RX VCO frequency ([T/R]X_VCO_Range = 01) TX and RX VCO frequency ([T/R]X_VCO_Range = 10) TX and ...
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S19252 Data Sheet Table 28: Performance Specifications (Continued) Parameter SONET J jitter transfer tr Internal RSCLK to TSD in RLPTIME mode with the use of external VCO SONET Jitter Generation - Measurements with Reference Clock Phase Noise as shown in ...
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Table 28: Performance Specifications (Continued) Parameter J jitter generation (9.95G rate) gen TSD (RLPTIME, XVCO 622 Mode, TAP2=5) J (10.709G rate) gen J jitter generation (9.95G rate) gen TSD (RLPTIME, XVCO 155 Mode, TAP2=5) J (10.709G rate) gen J jitter ...
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S19252 Data Sheet Table 28: Performance Specifications (Continued) Parameter Eye Mask X2 (Transmitter) Eye Mask Y1 (Transmitter) Eye Mask Y2 (Transmitter) J jitter generation gen TSD (Normal Mode with 622.08 MHz CSU REFCLK) J jitter generation gen TSD (Normal Mode ...
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Table 28: Performance Specifications (Continued) Parameter Eye Mask Y2 (Receiver) LOS Assert time LOS De-assert time LOS Assert Voltage LOS De-assert Voltage Reference clock frequency tolerance (CSU_REFCLK) CSU or CRU reference clock input duty cycle Reference clock rise and fall ...
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S19252 Data Sheet Table 28: Performance Specifications (Continued) Parameter High-Speed Input Sensitivity - SERDATIP/N serial input data (when driven single-ended) 9.95328 Gbps Data Rate High-Speed Input Sensitivity - SERDATIP/N serial input data (when driven single-ended) 10.709 Gbps Data Rate High-Speed ...
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Figure 15: S19252 with XFP System Performance Points 30 pin Connector B A S19252 D C Revision 5.03 AppliedMicro - Confidential and Proprietary E TOSA TX S19233 XFP Module F RX ROSA S19252 Data Sheet OC-192/10GE/10FC 65 ...
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S19252 Data Sheet Figure 16: XFI Transmitter Differential Output Compliance Mask -Y1 -Y2 0.0 Figure 17: XFI Receiver Differential Input Compliance Mask -Y1 -Y2 0.0 66 AppliedMicro - Confidential and Proprietary X1 X2 1-X2 ...
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Figure 18: XFI Receiver Input Telecom Sinusoidal Jitter Tolerance 15.2 1.7 0.17 0.05 0.01E-3 Figure 19: XFI Receiver Input Datacom Sinusoidal Jitter Tolerance 0.17 0.05 Revision 5.03 AppliedMicro - Confidential and Proprietary slope = -20 dB/decade 27.2 8 17.9E-3 0.4 ...
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S19252 Data Sheet Figure 20: 622.08 MHz CSU_REFCLK Phase Noise -105 -105 -110 -110 -115 -115 -120 -120 -125 -125 -130 -130 -135 -135 -140 -140 -145 -145 -150 -150 -155 -155 10,000 10,000 100,000 100,000 Figure 21: 155.52 MHz ...
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Electrical Specifications Table 29: Absolute Maximum and Minimum Ratings The following are the absolute maximum stress ratings for the S19252 device. Stresses beyond those listed may cause permanent damage to the device. Absolute maximum ratings are stress ratings only, and ...
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S19252 Data Sheet Table 30: Recommended Operating Conditions The device will meet all electrical specifications at junction temperature under bias of 125°C but part lifetime and reliability may be reduced recommended that prudent thermal management techniques are used ...
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Table 31: LVCMOS Input/Output Characteristics Parameter Description V Input high-voltage IH V Input low-voltage IL I Input high current IH I Input low current IL V Output high-voltage OH V Output low-voltage OL Table 32: High-Speed CML Input/Output Characteristics (TSD, ...
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S19252 Data Sheet Table 32: High-Speed CML Input/Output Characteristics (TSD, TSCLK, SERDATI) Parameter Description SDD11 Differential Input Return Loss (For XFP Applications) SCC11 Common Mode Input Return Loss (For XFP Applications) SCD11 Differential to Common Mode Input Conversion (For XFP ...
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Table 35: LVDS Input/Output Characteristics Parameter Description V Input high-voltage IH V Input low-voltage IL V Input common mode voltage IC V Single-ended input voltage swing INSINGLE V Differential input voltage swing INDIFF R Receiver differential input impedance IN V ...
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S19252 Data Sheet Table 36: Transmitter Timing Characteristics Parameter Duty Cycle 622 PICLK duty cycle = tD Duty Cycle PCLKP/N duty cycle Duty Cycle TX_155 MCK duty cycle t TSD set-up time with respect to rising edge of TSCLK. SUTSD ...
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Figure 22: Transmitter TSCLK to TSD Timing Characteristics TSD TSCLK Figure 23: Transmitter Timing Characteristics PINP/N[15:0] t SUPIN 622 MHz PICLK From Customer ASIC Revision 5.03 AppliedMicro - Confidential and Proprietary 1/DATA_RATE ps t SUTSD t HTSD 1607 ...
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S19252 Data Sheet Table 37: Receiver Timing Characteristics Parameter Duty Cycle POCLK duty cycle POCLK Jitter Generation (Normal Mode with CRU locked to 31 SERDATI, PRBS 2 RX_MCKP/N RX_MCKP/N duty cycle Duty Cycle T POUTP/N delay from POCLKP/N falling edge. ...
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Table 38: MDIO Timing Characteristics Parameter t Input set-up time from MDIO to MDC SU t Input hold time from MDIO to MDC H t MDC to MDIO Clock to data delay Delay MDC frequency Input Capacitance Bus Loading Capacitance ...
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S19252 Data Sheet ® Figure 25: I2C BUS Timing Diagram t HIGH SCL t LOW t HD,STA t t SU,STA HD,DAT t R SDA START ® Table 39: I2C BUS LVCMOS Input/Output & Timing Characteristics Parameter Description t Clock pulse ...
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Figure 26: SPI BUS Timing Diagram SSS V IH SCK MOSI MISO HI Table 40: SPI BUS Timing Characteristics Symbol Parameter f ...
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S19252 Data Sheet External Loop Filter Components Table 41: Transmit and Receive External Loop Filter Components, See Figure 27 REFCLK 155.52 MHz CSU_REFCLK 155.52 MHz CRU_REFCLK XVCO = 0 622.08 MHz CSU_REFCLK 622.08 MHz CRU_REFCLK XVCO = 0 155.52/622.08 MHz ...
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Figure 27: External Loop Filter Components TXCAP1 TXCAP2 S19252 Figure 28: FIFO Initialization PHERR PHINIT PCLK PICLK TRANSFER CLK (Internal PCLK) Revision 5.03 AppliedMicro - Confidential and Proprietary R1 RXCAP1 C1 RXCAP2 R2 S19252 S19252 Data Sheet ...
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S19252 Data Sheet Figure 29: Differential Voltage Measurement V(+) wrt to GND V(–) wrt to GND 0 V V(+) wrt to V(-) 0 V Note: WRT = With Respect To 82 AppliedMicro - Confidential and Proprietary V SINGLE V Diff ...
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Recommended Terminations Figure 30: S19252 Differential CML Output to +5 V/+3.3 V PECL Input AC Coupled Termination +1.2 V S19252 TSDP/N TSCLKP/N Figure 31: S19252 LVDS Driver to LVDS Input Termination + 19252 POUTP/N[ 15:0] POCLKP/N RX_ ...
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S19252 Data Sheet Figure 32 Differential PECL Driver to S19252 Differential CML Input AC Coupled Termination +5 V/ 3.3 V PECL Output Figure 33: +5 V/+3.3 V Differential PECL Driver to S19252 CML Reference Clock Input AC Coupled ...
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Figure 34: LVDS Driver to S19252 LVDS Inputs +3.3 V LVDS Output Revision 5.03 AppliedMicro - Confidential and Proprietary Zo=50 100 Zo=50 S19252 PINP/N[15:0] PICLKP/N S19252 Data Sheet +1 ...
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S19252 Data Sheet Document Revision History Revision Date 5.03 6/15/10 CHANGE PERTAINING TO PCN1304, “LOCKDET VALID WINDOW” • Page 59, Add conditions for PLL lockdet CHANGES UNRELATED TO PCN • Page 1, Clarification with General, Transmitter and Receiver Features • ...
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... Ordering Information Device Code S19252PBIDB S19252 - STS-192 SONET/SDH/FEC/GbE/FC 16-bit Transceiver with EDC Industrial Temp, Standard Package S19252PRID S19252 - STS-192 SONET/SDH/FEC/GbE/FC 16-bit Transceiver with EDC Industrial Temp, RoHS Compliant Package S19252 WW Technical Support: support@appliedmicro.com AppliedMicro reserves the right to make changes to its products, its datasheets, or related documentation, without notice and warrants its products solely pursuant to its terms and conditions of sale, only to substantially comply with the latest available datasheet. Please consult AppliedMicro’ ...