S19252PBIDB Applied Micro Circuits Corporation, S19252PBIDB Datasheet - Page 74

• Manufacturer Part Number: S19252PBIDB
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S19252PBIDB

• Lead Free Status / Rohs Status: Supplier Unconfirmed

S19252 Data Sheet
Table 36: Transmitter Timing Characteristics
74
Duty Cycle
Duty Cycle
Duty Cycle
t
t
t
t
t
FIFO drift
SUTSD
HTSD
SUPIN
HPIN
r
/t
Parameter
f
1.
1
1
200 mV p-p single-ended input swing
622 PICLK duty cycle = tD
PCLKP/N duty cycle
TX_155 MCK duty cycle
TSD set-up time with respect to rising edge of TSCLK.
See Figure 22.
TSD hold time with respect to rising edge of TSCLK.
See Figure 22.
PINP/N[15:0] set-up time with respect to rising edge of PICLKP.
See Figure 23.
PINP/N[15:0] hold time with respect to rising edge of PICLKP. See
Figure 23.
CML output rise and fall time (20% – 80%) - TSD (Low Swing)
CML output rise and fall time (20% – 80%) - TSD (High Swing)
LVDS input rise and fall time (20% – 80%)
LVDS output rise and fall time (20% – 80%)
LVCMOS output rise and fall Time (20% – 80%)
(10 pF load condition)
PCLK to PICLK drift after the FIFO is centered
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PICLK
Description
/T
0
Min
250
250
100
100
40
45
45
25
25
24
1
Typ
Max
300
250
60
55
55
35
15
2
Revision 5.03
cycles
PCLK
Units
ps
ps
ps
ps
ps
ps
ps
ps
ns
%
%
%