S19252PBIDB Applied Micro Circuits Corporation, S19252PBIDB Datasheet - Page 23

• Manufacturer Part Number: S19252PBIDB
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S19252PBIDB

• Lead Free Status / Rohs Status: Supplier Unconfirmed

User Defined BIST Pattern
(BIST_PTRN[15:0]) – Register
This is a user defined pattern which is output from the
transmit or the receive pattern generator. This pattern
is loaded on the rising edge of TX_BIST_EN or
RX_BIST_EN. The user defined pattern can be
selected by proper setting of the PRBS_SEL[1:0]. This
input is only accessible through the serial bus register.
Pattern Select (PRBS_SELECT[1:0]) –
Register
The pattern select bits select between the different
PRBS patterns and the user defined pattern. See
Table 13 for details. This input is only accessible
through the serial bus register.
Table 13: PRBS Pattern Select
The BOLD CELLS denote the default state
Bit Error Rate Range Select
(BER_SELECT[2:0]) – Register
The bit error rate range select bits selects the
appropriate bit error rate range for reporting the bit
error rate. See Table 14 for details. This input is only
accessible through the serial bus register.
Table 14: Bit Error Rate Range Select
Revision 5.03
PRBS_SELECT 1
BER_SELECT
0
0
0
0
0
1
0
0
1
1
0
1
0
PRBS_SELECT 0
Bit Error Rate Exponent/
BER_COUNT[11:0] * 10
BER_COUNT[11:0] * 10
BER_COUNT[11:0] * 10
Terminal Count = 10
Terminal Count = 10
Terminal Count = 10
0
1
0
1
Terminal Count
AppliedMicro - Confidential and Proprietary
PRBS Pattern
User Defined
PRBS 23
PRBS 31
PRBS 7
6
7
8
-6
-7
-8
Table 14: Bit Error Rate Range Select (Continued)
The BOLD CELLS denote the default state
Bit Error Rate Reset (BER_RSTB) –
Register
This input selects whether the BER_COUNT[11:0] is
reset after each terminal count. When active (high),
BER_COUNT[11:0] is not reset after each terminal
count (transition on TERM_COUNT), but instead
continues to accrue errors. This input is only accessible
through the serial bus register.
Clock Stop Value (CLKSTOP_VAL) –
Register
The Clock Stop Value (CLKSTOP_VAL) register bit,
specifies the steady state value when a clock is “killed”
or disabled. A high value disables the killed clock to a
high steady state, a low value disables the killed clock
to a low steady state value. This input is only
accessible by serial bus control.
BER_SELECT
0
0
1
1
1
0
1
0
0
1
X
0
1
0
1
BER_COUNT[11:0] * 10
BER_COUNT[11:0] * 10
BER_COUNT[11:0] * 10
Bit Error Rate Exponent/
BER_COUNT[11:0] * 10
BER_COUNT[11:0] * 10
Terminal Count = 10
Terminal Count = 10
Terminal Count = 10
Terminal Count = 10
Terminal Count = 10
Terminal Count
S19252 Data Sheet
10
10
12
6
9
-10
-11
-12
-6
-9
23