S19252PBIDB Applied Micro Circuits Corporation, S19252PBIDB Datasheet - Page 18

• Manufacturer Part Number: S19252PBIDB
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S19252PBIDB

• Lead Free Status / Rohs Status: Supplier Unconfirmed

S19252 Data Sheet
Kill Parallel Output Clock (KILLPOCLK)
– Register
The active high Kill Parallel Output Clock (KILLPOCLK)
signal, when asserted high, will force the POCLK
output to a state specified by the CLKSTOP_VAL
register bit. This input may be programmed to logic ‘0’
for normal operation. This input is only accessible
through the serial bus register.
Kill Parallel Output Data (KILLPOUTB)
– Register
The active low Kill Parallel Output Data (KILLPOUTB)
signal, when asserted low, will force the POUT[15:0]
output to a logic ‘0’ state. This input may be
programmed to logic ‘1’ for normal operation. This input
is only accessible through the serial bus register.
Kill Parallel Output MCK Clock
(KILLRXMCK) – Register
The active high Kill Parallel Output 622MCK Clock
(KILLRXMCK) signal, when asserted high, will force
the 622MCK output to a state specified by the
CLKSTOP_VAL register bit. This input may be
programmed to logic ‘0’ for normal operation. This input
is only accessible through the serial bus register.
Receive Built-In Self Test Enable
(RX_BIST_EN) – Register
This active high input enables the receive built-in self
test mode. For normal system operation, RX_BIST_EN
should be programmed to logic ‘0’. The S19252 goes in
the BIST mode when RX_BIST_EN is programmed to
logic high. Once the RX_BIST_EN is programmed to
logic high, the PRBS generator will start sending the
PRBS/user defined pattern (see Table 13 for details)
through the parallel outputs, and the checker will be
activated but will not start checking for the valid data
pattern until TX_LOCKDET is active. This input is only
accessible through the serial bus register. Note - While
RX BIST is enabled the parallel output bus will not
provide a RX_DATA_SWAP even if RX_DATA_SWAP
is enabled.
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Receive Built-In Self Test Clear
(RX_BIST_CLR) – Register
This active high level sensitive input clears the receive
Built-In Self Test Error (RX_BIST_ERR). For normal
system
programmed to logic ‘0’. The RX_BIST_ERR flag can
be cleared by asserting RX_BIST_CLR in the BIST
mode
RX_BIST_CLR is an active high level sensitive input. In
order
RX_BIST_ERR flag, the RX_BIST_CLR must be
asserted high. This input is only accessible through the
serial bus register.
LOS Threshold Assert (LOS_VTH_AST
[7:0]) – Register
The LOS Threshold Assert (LOS_VTH_AST[7:0])
inputs control the LOS assert threshold for the high
speed serial input. The 8-bit control register set the
LOS assert voltage where the Loss of signal condition
is declared. These inputs are only accessible through
the serial bus registers
LOS Threshold De-Assert
(LOS_VTH_DST [7:0]) – Register
The LOS Threshold De-Assert (LOS_VTH_DST[7:0])
inputs control the LOS de-assert threshold for the high
speed serial input. The 8-bit control register set the
LOS de-assert voltage where the Loss of signal
condition is declared. These inputs are only accessible
through the serial bus registers
Phase Adjust (PHASE_ADJ[2:0]) –
Register
The Phase Adjust (PHASE_ADJ[2:0]) inputs control
the phase offset between the high speed recovered
data and clock for improved bit error rate and link
budgets. These registers are not adaptively controlled.
See Table 8 for details of the phase adjust settings.
These inputs are only accessible through the serial bus
registers.
for
or
operation,
by
the
resetting
receive
RX_BIST_CLR
checker
(RSTB)
to
the
Revision 5.03
should
clear
S19252.
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