PEF82902FV11XP Lantiq, PEF82902FV11XP Datasheet - Page 11

• Manufacturer Part Number: PEF82902FV11XP
• Manufacturer: Lantiq

Specifications of PEF82902FV11XP

• Lead Free Status / Rohs Status: Supplier Unconfirmed

List of Figures
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Data Sheet
State Machine LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Interrupt Structure S-Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Activation Initiated by Exchange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Activation Initiated by TE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Activation Initiated by NT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Complete Deactivation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Loop 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Test Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
External Loop at the S/T-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Complete Loopback Options in NT-Mode . . . . . . . . . . . . . . . . . . . . . 106
Loopbacks Featured by Register LOOP . . . . . . . . . . . . . . . . . . . . . . 107
Power Supply Blocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
External Circuitry U-Transceiver with External Hybrid . . . . . . . . . . . . 109
External Circuitry S-Interface Transmitter . . . . . . . . . . . . . . . . . . . . . 112
External Circuitry S-Interface Receiver . . . . . . . . . . . . . . . . . . . . . . . 112
Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Address Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
T-SMINT‚I Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . 115
Maximum Sinusoidal Ripple on Supply Voltage
Input/Output Waveform for AC Tests. . . . . . . . . . . . . . . . . . . . . . . . . 165
IOM®-2 Interface - Bit Synchronization Timing . . . . . . . . . . . . . . . . . 166
IOM
Serial Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Microprocessor Read Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Microprocessor Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Multiplexed Address Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Non-Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Microprocessor Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Microprocessor Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Non-Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Reset Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Undervoltage Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
NTC-Q Compatible State Machine Q-SMINT‚I: 2B1Q . . . . . . . . . . . . 181
Simplified State Machine Q-SMINT‚I: 2B1Q . . . . . . . . . . . . . . . . . . . 182
IEC-T/NTC-T Compatible State Machine T-SMINT‚I: 4B3T. . . . . . . . 183
Interrupt Structure U-Transceiver Q-SMINT‚I: 2B1Q . . . . . . . . . . . . . 185
Interrupt Structure U-Transceiver T-SMINT‚I: 4B3T. . . . . . . . . . . . . . 186
External Circuitry Q- and T-SMINT‚I . . . . . . . . . . . . . . . . . . . . . . . . . 190
®
-2 Interface - Frame Synchronization Timing . . . . . . . . . . . . . . 166
. . . . . . . . . . . . . . . 164
PEF 82902
2001-11-09
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