PEF82902FV11XP Lantiq, PEF82902FV11XP Datasheet - Page 39

• Manufacturer Part Number: PEF82902FV11XP
• Manufacturer: Lantiq

Specifications of PEF82902FV11XP

• Lead Free Status / Rohs Status: Supplier Unconfirmed

2.3
The T-SMINT
according to the IOM
2.3.1
The IOM
rising edge of FSC indicates the start of an IOM
signals synchronize the data transfer on both data lines DU and DD. The DCL is twice
the bit rate, the BCL rate is equal to the bit rate. The bits are shifted out with the rising
edge of the first DCL clock cycle and sampled at the falling edge of the second clock
cycle. With BCL the bits are shifted out with the rising edge and sampled with the falling
edge of the single clock cycle.
The IOM
registerThe FSC signal is an 8 kHz frame sync signal. The number of PCM timeslots on
the receive and transmit lines is determined by the frequency of the DCL clock (or BCL),
with the 1.536 MHz (BCL=768 kHz) clock 3 channels consisting of 4 timeslots each are
available.
IOM
The frame structure on the IOM
clock of 1.536 MHz (or BCL=768 kHz) and if TIC bus is not disabled (IOM_CR.TIC_DIS)
is shown in
•
Figure 10
Data Sheet
®
-2 Frame Structure of the T-SMINT
â
â
-2 interface consists of four lines: FSC, DCL, DD, DU and optionally BCL. The
-2 interface can be enabled/disabled with the DIS_IOM bit in the IOM_CR
IOM -2 Interface
IOM
Figure
â
IOM -2 Frame Structure of the T-SMINT
I supports the IOM
â
-2 Functional Description
10.
â
-2 Reference Guide [12].
â
-2 data ports (DU,DD) of the T-SMINT
â
-2 interface in terminal mode (DCL=1.536 MHz)
27
â
I
â
-2 frame. The DCL and the BCL clock
â
I
Functional Description
â
I with a DCL
PEF 82902
macro_19
2001-11-09