PEF82902FV11XP Lantiq, PEF82902FV11XP Datasheet - Page 127

• Manufacturer Part Number: PEF82902FV11XP
• Manufacturer: Lantiq

Specifications of PEF82902FV11XP

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Figure 59
After the T-SMINT
must read first the T-SMINT
service routine. The INT pin of the T-SMINT
are cleared. Therefore, it is possible that the INT pin is still active when the interrupt
service routine is finished.
Each interrupt indication of the interrupt status registers can selectively be masked by
setting the respective bit in the MASK register.
For some interrupt controllers or hosts it might be necessary to generate a new edge on
the interrupt line to recognize pending interrupts. This can be done by masking all
interrupts at the end of the interrupt service routine (writing FF
and writing back the old mask to the MASK register.
Data Sheet
MASK
WOV
MOS
CIC
INT
ST
U
S
1
1
T-SMINT
WOV
ISTA
MOS
CIC
ST
U
0
S
0
â
MASKU
I has requested an interrupt by setting its INT pin to low, the host
RDS
1ms
CI
1
1
1
1
1
â
I Interrupt Status Registers
â
I interrupt status register (ISTA) in the associated interrupt
ISTAU
RDS
1ms
CI
CI1E
CIX1
0
0
0
0
0
115
STOV20
STOV11
STOV21
STOV10
â
MSTI
STI11
STI10
STI21
STI20
I remains active until all interrupt sources
CIC0
CIC1
CIR0
STOV20
STOV11
STOV21
STOV10
STI11
STI10
STI21
STI20
MASKS
STI
MOCR
MRE
SQC
SQW
MIE
RIC
LD
H
into the MASK register)
Register Description
ACK10
ACK11
ACK21
ACK20
ISTAS
ASTI
MOSR
MER
SQW
MDR
MDA
MAB
SQC
PEF 82902
RIC
LD
2001-11-09