PEF82902FV11XP Lantiq, PEF82902FV11XP Datasheet - Page 47

• Manufacturer Part Number: PEF82902FV11XP
• Manufacturer: Lantiq

Specifications of PEF82902FV11XP

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Monitoring Data
Figure 16
simultaneously. For monitoring on DU and/or DD the channel registers with even
numbers (CDA10, CDA20) are assigned to time slots with even numbers TS(2n) and the
channel registers with odd numbers (CDA11, CDA21) are assigned to time slots with odd
numbers TS(2n+1). The user has to take care of this restriction by programming the
appropriate time slots.
This mode is only valid if two blocks (e.g. both transceivers) are programmed to these
timeslots and communicating via IOM
However, if only one block is programmed to this timeslot the timeslots for CDAx0 and
CDAx1 can be programmed completely independently.
•.
Figure 16
Monitoring TIC Bus
Monitoring the TIC bus (TS11) is handled as a special case. The TIC bus can be
monitored with the registers CDAx0 by setting the EN_TBM (Enable TIC Bus Monitoring)
bit in the control registers CRx. The TSDPx0 must be set to 08
Data Sheet
a) Monitoring Data
gives an example for monitoring of two IOM
Example for Monitoring Data
CDA_CR1.
CDA_CR2.
EN_O:
EN_O:
EN_I:
EN_I:
DPS:
DPS:
TSS:
TSS:
CDA20
CDA10
TS(2n)
â
TS(2n)
’0’
’0’
’1’
’1’
’1’
’0’
-2.
35
â
-2 time slots each on DU or DD
TS(2n+1)
TS(2n+1)
CDA11
CDA21
’0’
’1’
’0’
’1’
’1’
’0’
Functional Description
h
for monitoring from DU
PEF 82902
DD
DU
2001-11-09