PEF82902FV11XP Lantiq, PEF82902FV11XP Datasheet - Page 149

• Manufacturer Part Number: PEF82902FV11XP
• Manufacturer: Lantiq

Specifications of PEF82902FV11XP

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Bit 7..0
Each interrupt source in the ISTA register can be selectively masked by setting the
corresponding bit in MASK to ‘1’. Masked interrupt status bits are not indicated when
ISTA is read. Instead, they remain internally stored and pending, until the mask bit is
reset to ‘0’.
Note: In the event of a C/I channel change, CIC is set in ISTA even if the corresponding
4.6.3
MODE1
Value after reset: 04
MCLK
Data Sheet
mask bit in MASK is active, but no interrupt is generated.
U
7
7
MODE1 - Mode1 Register
Mask bits
0 =
1 =
Master Clock Frequency
The Master Clock Frequency bits control the microcontroller clock output
depending on MODE1.CDS = ’0’ or ’1’ (Table
00 =
01 =
10 =
11 =
MCLK
ST
Interrupt is not masked
Interrupt is masked
MODE1.CDS = ’0’
3.84 MHz
0.96 MHz
7.68 MHz
disabled
H
CDS
CIC
WTC1
1
read/write
137
MODE1.CDS = ’1’
7.68 MHz
1.92 MHz
15.36 MHz
disabled
WTC2
WOV
Table
CFS
S
2.1.3).
Register Description
RSS2
MOS
Address:
PEF 82902
2001-11-09
RSS1
0
1
0
3D
H