PEF82902FV11XP Lantiq, PEF82902FV11XP Datasheet - Page 150

• Manufacturer Part Number: PEF82902FV11XP
• Manufacturer: Lantiq

Specifications of PEF82902FV11XP

• Lead Free Status / Rohs Status: Supplier Unconfirmed

CDS
WTC1, 2
CFS
RSS2,
RSS1
Data Sheet
Clock Divider Selection
0 =
1 =
Watchdog Timer Control 1, 2
After the watchdog timer mode has been selected (RSS = ‘11’) the
watchdog timer is started. During every time period of 128 ms the
microcontroller has to program the WTC1 and WTC2 bit in the following
sequence
10
01
to reset and restart the watchdog timer.
If not, the timer expires and a WOV-interrupt (ISTA Register) together with
a reset out pulse on pin RSTO is generated.
The watchdog timer runs only when the internal IOM
i.e. the watchdog timer is dead when bit CFS = 1 and the U and S-
transceivers are in state power down.
Configuration Select
0 =
1 =
Reset Source Selection 2,1
The T-SMINT
00 =
01 =
10 =
11 =
The 15.36 MHz oscillator clock divided by two is input to the MCLK
prescaler
The 15.36 MHz oscillator clock is input to the MCLK prescaler.
first step
second step
The IOM
“Deactivated State” of the U-transceiver and the S-transceiver
included.
The IOM
“Deactivated State” of the U-transceiver and the S-transceiver.
C/I Code Change
--
x
--
(Chapter
â
I reset sources can be selected according to the table below.
®
®
-2 interface clock and frame signals are always active,
-2 interface clocks and frame signals are inactive in the
2.2):
RSTO disabled (high impedance)
138
--
--
x
Watchdog Timer
®
Register Description
-2 clocks are active,
POR/UVD and RST
x
x
x
PEF 82902
2001-11-09