PEF82902FV11XP Lantiq, PEF82902FV11XP Datasheet - Page 142

• Manufacturer Part Number: PEF82902FV11XP
• Manufacturer: Lantiq

Specifications of PEF82902FV11XP

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Important: This register is used only if the Layer 1 state machine of the device is disabled
(S_CONF0:L1SW = 1) and implemented in software! With the layer 1 state machine
enabled, the signals from this register are automatically evaluated.
RINF
ICV
FSYN
LD
4.5.4
S_ CMD
Value after reset: 08
Data Sheet
7
7
S_CMD - S-Transceiver Command Register
Receiver INFO
00 =
01 =
10 =
11 =
Illegal Code Violation
0 =
1 =
Frame Synchronization State
0 =
1 =
Level Detection
0 =
1 =
RINF
XINF
Received INFO 0 (no signal)
Received any signal except INFO 0 or INFO 3
reserved
Received INFO 3
No illegal code violation is detected.
Illegal code violation (ANSI T1.605) in data stream is detected.
The S/T receiver is not synchronized.
The S/T receiver has synchronized to the framing bit F.
No receive signal has been detected on the line.
Any receive signal has been detected on the line.
H
0
DPRIO
ICV
read/write
130
0
1
FSYN
PD
Register Description
LP_A
Address:
0
PEF 82902
2001-11-09
LD
0
0
0
34
H