PEF82902FV11XP Lantiq, PEF82902FV11XP Datasheet - Page 66

• Manufacturer Part Number: PEF82902FV11XP
• Manufacturer: Lantiq

Specifications of PEF82902FV11XP

• Lead Free Status / Rohs Status: Supplier Unconfirmed

•
Figure 29
2.3.5.4
In intelligent NT applications (selected via register S_MODE.MODE2-0) the T-SMINT
has to share the upstream D-channel with one or more D-channel controllers on the
IOM
The S-transceiver incorporates an elaborate state machine for D-channel priority
handling on IOM
arbitration mechanism as on the S interface (writing D-bits, reading back E-bits) is
performed for all D-channel sources on IOM
guaranteed for all D-channel sources on both the S interface and the IOM
The access to the upstream D-channel is handled via the S/G bit for the HDLC
controllers and via E-bit for all connected terminals on S (E-bits are inverted to block the
terminals on S). Furthermore, if more than one HDLC source is requesting D-channel
access on IOM
The arbiter permanently counts the “1s” in the upstream D-channel on IOM
necessary number of “1s” is counted and an HDLC controller on IOM
upstream D-channel access (BAC bit is set to 0), the arbiter allows this D-channel
controller immediate access and blocks other TEs on S (E-bits are inverted). Similar as
on the S-interface the priority for D-channel access on IOM
10 (S_CMD.DPRIO).
The configuration settings of the T-SMINT
summarized in
Data Sheet
â
DD
-2 interface and with all connected TEs on the S interface.
D-Channel Arbitration
B1
Structure of Last Octet of Ch2 on DD
â
Table
-2 the TIC bus mechanism is used (see
â
B2
-2
12.
(Chapter
MON
0
D CI0
2.3.5.5). For the access to the D-channel a similar
MR
MX
IC1
Stop/Go
IC2
54
â
-2. Due to this an equal and fair access is
S/G A/B
â
MON1
I in intelligent NT applications are
CI1
Available/Blocked
Chapter
â
MR
MX
-2 can be configured to 8 or
Functional Description
2.3.5.2).
â
â
S/G
PEF 82902
-2 interface.
-2 requests
ITD09693.vsd
2001-11-09
â
-2. If the
A/B
â
I