PEF82902FV11XP Lantiq, PEF82902FV11XP Datasheet - Page 155

• Manufacturer Part Number: PEF82902FV11XP
• Manufacturer: Lantiq

Specifications of PEF82902FV11XP

• Lead Free Status / Rohs Status: Supplier Unconfirmed

EN_O1,
EN_O0
SWAP
4.7.4
S_CR
Value after reset: FF
CI_CS
Data Sheet
7
1
This bit is used to select the IOM channel to which the S-transceiver C/I-
channel is related to.
S_CR - Control Register S-Transceiver Data
0 =
1 =
Enable Output CDAx1, CDAx0
0 =
1 =
Swap Inputs
0 =
1 =
C/I Channel Selection
0 =
1 =
CI_CS
The input of the CDAx1, CDAx0 register is disabled
The input of the CDAx1, CDAx0 register is enabled
The output of the CDAx1, CDAx0 register is disabled
The output of the CDAx1, CDAx0 register is enabled
The time slot and data port for the input of the CDAxy register is
defined by its own TSDPxy register. The data port for the CDAxy
input is vice versa to the output setting for CDAxy.
The input (time slot and data port) of the CDAx0 is defined by the
TSDP register of CDAx1 and the input of CDAx1 is defined by the
TSDP register of CDAx0. The data port for the CDAx0 input is vice
versa to the output setting for CDAx1. The data port for the CDAx1
input is vice versa to the output setting for CDAx0. The input
definition for time slot and data port CDAx0 are thus swapped to
CDAx1 and for CDAx1 to CDAx0. The outputs are not affected by
the SWAP bit.
C/I-channel in IOM-channel 0
C/I-channel in IOM-channel 1
H
EN_D
EN_B2R EN_B1R EN_B2X EN_B1X
read/write
143
Register Description
Address:
PEF 82902
2001-11-09
D_CS
0
51
H