MT41J256M8DA-125:H Micron Technology Inc, MT41J256M8DA-125:H Datasheet - Page 11

• Manufacturer Part Number: MT41J256M8DA-125:H
• Manufacturer: Micron Technology Inc

Specifications of MT41J256M8DA-125:H

• Lead Free Status / Rohs Status: Supplier Unconfirmed

State Diagram
Figure 2: Simplified State Diagram
Power
applied
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
ACT = ACTIVATE
MPR = Multipurpose register
MRS = Mode register set
PDE = Power-down entry
PDX = Power-down exit
PRE = PRECHARGE
From any
state
Power
on
RESET
procedure
Reset
WRITE
CKE L
Initialization
calibration
WRITE AP
Writing
power-
Writing
Active
down
PREA = PRECHARGE ALL
READ = RD, RDS4, RDS8
READ AP = RDAP, RDAPS4, RDAPS8
REF = REFRESH
RESET = START RESET PROCEDURE
SRE = Self refresh entry
ZQCL
ZQ
ZQCL/ZQCS
WRITE
PDX
PDE
PRE, PREA
WRITE AP
WRITE AP
11
WRITE
Precharging
MRS, MPR,
Activating
MRS
leveling
PRE, PREA
active
write
Bank
Idle
ACT
READ
READ AP
READ AP
Micron Technology, Inc. reserves the right to change products or specifications without notice.
PRE, PREA
PDE
PDX
READ
2Gb: x4, x8, x16 DDR3 SDRAM
SRX
SRX = Self refresh exit
WRITE = WR, WRS4, WRS8
WRITE AP = WRAP, WRAPS4, WRAPS8
ZQCL = ZQ LONG CALIBRATION
ZQCS = ZQ SHORT CALIBRATION
REF
Precharge
SRE
Reading
Reading
READ AP
power-
down
© 2006 Micron Technology, Inc. All rights reserved.
CKE L
READ
State Diagram
Refreshing
refresh
Self
Automatic
sequence
Command
sequence
CKE L