MT41J256M8DA-125:H Micron Technology Inc, MT41J256M8DA-125:H Datasheet - Page 187

• Manufacturer Part Number: MT41J256M8DA-125:H
• Manufacturer: Micron Technology Inc

Specifications of MT41J256M8DA-125:H

• Lead Free Status / Rohs Status: Supplier Unconfirmed

RESET Operation
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
The RESET signal (RESET#) is an asynchronous signal that triggers any time it drops
LOW, and there are no restrictions about when it can go LOW. After RESET# goes LOW,
it must remain LOW for 100ns. During this time, the outputs are disabled, ODT (R
turns off (High-Z), and the DRAM resets itself. CKE should be brought LOW prior to RE-
SET# being driven HIGH. After RESET# goes HIGH, the DRAM must be reinitialized as
though a normal power-up was executed. All refresh counters on the DRAM are reset,
and data stored in the DRAM is assumed unknown after RESET# has gone LOW.
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2Gb: x4, x8, x16 DDR3 SDRAM
© 2006 Micron Technology, Inc. All rights reserved.
RESET Operation
TT
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