MT41J256M8DA-125:H Micron Technology Inc, MT41J256M8DA-125:H Datasheet - Page 140

• Manufacturer Part Number: MT41J256M8DA-125:H
• Manufacturer: Micron Technology Inc

Specifications of MT41J256M8DA-125:H

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Figure 55: READ Latency (AL = 5, CL = 6)
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
BC4
DQS, DQS#
Command
CK#
DQ
CK
ACTIVE n
T0
READ n
(MIN) = CL, a typical application using this feature sets AL = CL - 1
t
internally to the DDR3 SDRAM device. READ latency (RL) is controlled by the sum of
the AL and CAS latency (CL), RL = AL + CL. WRITE latency (WL) is the sum of CAS
WRITE latency and AL, WL = AL + CWL (see Mode Register 2 (MR2) (page 141)). Exam-
ples of READ and WRITE latencies are shown in Figure 55 (page 140) and Figure 56
(page 141).
T1
CK. The READ or WRITE command is held for the time of the AL before it is released
t RCD (MIN)
AL = 5
NOP
T2
RL = AL + CL = 11
NOP
T6
140
CL = 6
Micron Technology, Inc. reserves the right to change products or specifications without notice.
T11
NOP
Indicates A Break in
Time Scale
2Gb: x4, x8, x16 DDR3 SDRAM
NOP
T12
Mode Register 1 (MR1)
DO
n
© 2006 Micron Technology, Inc. All rights reserved.
Transitioning Data
n + 1
DO
t
CK =
NOP
T13
n + 2
DO
t
RCD (MIN) - 1
n + 3
DO
Don’t Care
NOP
T14