MT41J256M8DA-125:H Micron Technology Inc, MT41J256M8DA-125:H Datasheet - Page 163
MT41J256M8DA-125:H
Manufacturer Part Number
MT41J256M8DA-125:H
Description
Manufacturer
Micron Technology Inc
Datasheet
1.MT41J256M8DA-125H.pdf
(210 pages)
Specifications of MT41J256M8DA-125:H
Lead Free Status / Rohs Status
Supplier Unconfirmed
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Figure 78: Data Strobe Timing – READs
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
early strobe
DQS, DQS#
DQS, DQS#
late strobe
CK#
CK
t LZ (DQS) MIN
T0
t LZ (DQS) MAX
t RPRE
t
parameters are referenced to a specific voltage level which specifies when the device
output is no longer driving
(DQ). Figure 79 (page 164) shows a method to calculate the point when the device is no
longer driving
ing the signal at two different voltages. The actual voltage measurement points are not
critical as long as the calculation is consistent. The parameters
(DQS), and
HZ and
t DQSCK (MIN)
t RPRE
Bit 0
RL measured
to this point
t
LZ transitions occur in the same access time as valid data transitions. These
T1
t QSH
t DQSCK (MAX)
t
HZ (DQ) are defined as single-ended.
Bit 0
Bit 1
t
HZ (DQS) and
t QSH
t DQSCK (MIN)
t QSL
Bit 1
Bit 2
t QSL
T2
t QSH
t DQSCK (MAX)
t
HZ (DQS) and
Bit 2
163
Bit 3
t
HZ (DQ) or begins driving
t QSH
t DQSCK (MIN)
t QSL
Bit 4
Bit 3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t QSL
T3
t DQSCK (MAX)
t
HZ (DQ) or begins driving
Bit 4
Bit 5
2Gb: x4, x8, x16 DDR3 SDRAM
t DQSCK (MIN)
Bit 5
Bit 6
T4
t
t DQSCK (MAX)
LZ (DQS),
Bit 6
Bit 7
© 2006 Micron Technology, Inc. All rights reserved.
t HZ (DQS) MIN
t RPST
t
LZ (DQS),
Bit 7
t
LZ (DQ) by measur-
t
t RPST
LZ (DQS),
T5
t HZ (DQS) MAX
t
LZ (DQ),
t
LZ
t
HZ
T6
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