AM79C961AVIW AMD (ADVANCED MICRO DEVICES), AM79C961AVIW Datasheet - Page 103

• Manufacturer Part Number: AM79C961AVIW
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C961AVIW

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / Rohs Status: Not Compliant

CSR12: Physical Address Register, PADR[15:0]
Bit
15-0 PADR[15:0]
CSR13: Physical Address Register, PADR[31:16]
Bit
15-0PADR[31:16]
CSR14: Physical Address Register, PADR[47:32]
Bit
15-0 PADR[47:32]
CSR15: Mode Register
Bit
Name
Name
Name
Name
Read/write
when STOP or SPND bits are
set.
Physical
PADR[15:0].
initialized either automatically by
loading the initialization block or
directly by an I/O write to this
register. The PADR bits are
transmitted PADR[0] first and
PADR[47] last.
Read/write
when STOP or SPND bits are
set.
Physical
PADR[31:16]. Undefined until
initialized either automatically by
loading the initialization block or
directly by an I/O write to this
register. The PADR bits are
transmitted PADR[0] first and
PADR[47] last.
Read/write
when STOP or SPND bits are
set.
Physical
PADR[47:32]. Undefined until
initialized either automatically by
loading the initialization block or
directly by an I/O write to this
register. The PADR bits are
transmitted PADR[0] first and
PADR[47] last.
Read/write
when STOP or SPND bits are
set.
This register’s fields are loaded
during the PCnet-ISA II controller
initialization routine with the cor-
responding Initialization Block
values. The register can also be
loaded directly by an I/O write.
Description
Description
Description
Description
Address
Address
Address
accessible
accessible
accessible
accessible
Undefined
Register,
Register,
Register,
until
only
only
only
only
Am79C961A
15
14
13
12
11
DLNKTST
DRCVBC
DRCVPA
PROM
DAPC
Activating the RESET pin clears
all bits of CSR15 to zero.
Promiscuous Mode.
When PROM = “1", all incoming
receive frames are accepted.
Read/write
when STOP or SPND bits are
set.
DisableReceiveBroadcast
When set, disables the PCnet-ISA
II controller from receiving broad-
cast messages. Used for proto-
cols that do not support broadcast
addressing, except as a function
of multicast. DRCVBC is cleared
by activation of the RESET pin
(broadcast messages will be
received).
Read/write
when STOP or SPND bits are
set.
Disable Receive Physical Ad-
dress. When set, the physical
address detection (Station or
node ID) of the PCnet-ISA II con-
troller will be disabled. Frames
addressed
individual physical address will
not be recognized (although the
frame may be accepted by the
EADI mechanism).
Read/write
when STOP or SPND bits are
set.
Disable
DLNKTST = “1", monitoring of
Link Pulses is disabled. When
DLNKTST = “0", monitoring of
Link Pulses is enabled. This bit
only has meaning when the
10BASE-T network interface is
selected.
Read/write
when STOP or SPND bits are
set.
Disable
Correction. When DAPC = “1",
the 10BASE-T receive polarity
reversal algorithm is disabled.
Likewise, when DAPC = “0", the
polarity reversal algorithm is
enabled.
This bit only has meaning when
the 10BASE-T network interface
is selected.
Read/write
when STOP or SPND bits are
set.
Link
Automatic
to
accessible
accessible
accessible
accessible
accessible
Status.
the
Polarity
nodes
.
When
only
only
only
only
only
103