AM79C961AVIW AMD (ADVANCED MICRO DEVICES), AM79C961AVIW Datasheet - Page 64

• Manufacturer Part Number: AM79C961AVIW
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C961AVIW

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / Rohs Status: Not Compliant

descriptor accesses are always either 3, 2, or 1 cycles
long, depending on which descriptor operation is being
performed.
If the TIMER bit is set, the 3, 2, or 1 cycles required in
a descriptor access may be performed as a part of a
bus mastership period in which any combination of
descriptor reads and writes and buffer reads and writes
are performed. When the TIMER bit is set, the Bus
Activity Timer (CSR82) and the bus access require-
ments of the PCnet-ISA II govern the operations per-
formed during a single bus mastership period.
3. FIFO DMA Transfers
FIFO DMA transfers occur when the PCnet-ISA II
microcode determines that transfers to and/or from the
FIFOs are required. Once the PCnet-ISA II BIU has
been granted bus mastership, it will perform a series of
consecutive transfer cycles before relinquishing the
bus.
When the Bus Activity Timer is disabled by clearing the
TIMER (CSR4, bit 13) bit, all FIFO DMA transfers
within a bus mastership period will be either read or
write cycles, and all transfers will be to adjacent,
ascending addresses. When the Bus Activity Timer is
enabled by setting the TIMER bit, DMA transfers within
a bus mastership period may consist of any mixture of
read and write cycles, without restriction on the
address ordering. This mode of operation allows the
PCnet-ISA II to accomplish more during each bus
ownership period.
The number of data transfer cycles contained within a
single bus mastership period is in general dependent
on the programming of the DMAPLUS (CSR4, bit 14)
and the TIMER (CSR4, bit 13) options. Several other
factors will also affect the length of the bus mastership
period. The possibilities are as follows:
If DMAPLUS = 0 and TIMER = 0, a maximum of 16
transfers to or from the FIFO will be performed by
default. This default value may be changed by writing
to the DMA Burst Register (CSR80, bits 7:0). Since
TIMER = 0, all FIFO DMA transfers within a bus mas-
tership period will be either read or write cycles, and all
transfers will be to adjacent, ascending addresses.
Note that DMAPLUS = 0 merely sets a maximum value
for the number of FIFO transfers that may occur during
one bus mastership period. The minimum number of
transfers in the bus mastership period will be deter-
mined by the settings of the FIFO watermarks and the
conditions of the FIFOs, and the value of the Bus Activ-
ity Timer (CSR82) if the TIMER bit is set.
If DMAPLUS = 1 and TIMER = 0, the bus mastership
period will continue until the transmit FIFO is filled to its
high threshold (read transfers) or the receive FIFO is
emptied to its low threshold (write transfers). Other
variables may also affect the end point of the bus mas-
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Am79C961A
tership period in this mode, including the particular con-
ditions existing within the FIFOs, and receive and
transmit status conditions. Since TIMER = 0, all FIFO
DMA transfers within a bus mastership period will be
either read or write cycles, and all transfers will be to
adjacent, ascending addresses.
If TIMER = 1, the bus mastership period will continue
until all “pending bus operations” are completed or until
the Bus Activity Timer value (CSR82) has expired.
These bus operations may consist of any mixture of
descriptor and buffer read and write accesses. If DMA-
PLUS = 1, “pending bus operations” includes any de-
scriptor accesses and buffer accesses that need to be
performed. If DMAPLUS = 0, “pending bus operations”
include any descriptor accesses that need to be per-
formed and any buffer accesses that need to be per-
formed up to the limit specified by the DMA Burst
Register (CSR80, bits 7:0).
Note that when TIMER=1, following a last bus transac-
tion during a bus mastership period, the PCnet-ISA II
may keep ownership of the bus for up to approximately
1 s. The PCnet-ISA II determines whether there are
further pending bus operations by waiting approxi-
mately 1 s after the completion of every bus operation
(e.g. a descriptor or FIFO access). If, during the 1 s
period, no further bus operations are requested by the
internal Buffer Management Unit, the PCnet-ISA II
determines that there are no further pending opera-
tions and gives up bus ownership. This 1 s of unused
bus ownership time is more than made up for by the
efficiency gained by being able to perform any mixture
of descriptor and buffer read and write accesses during
a single bus ownership period.
The FIFO thresholds are programmable (see descrip-
tion of CSR80), as are the DMA Burst Register and Bus
Activity Timer values. The exact number of transfer
cycles in the case of DMAPLUS = 1 will be dependent
on the latency of the system bus to the PCnet-ISA II
controller’s DMA request and the speed of bus opera-
tion, but will be limited by the value in the Bus Activity
Timer register (if the TIMER bit is set), the FIFO condi-
tion, and receive and transmit status. Barring a
time-out by either of these registers, or exceptional re-
ceive and transmit events, or an end of packet signal
from the FIFO, the FIFO watermark settings and the
extent of Bus Grant latency will be the major factors de-
termining the number of accesses performed during
any given arbitration cycle when DMAPLUS = 1.
The IOCHRDY response of the memory device will
a l s o a f fe c t t h e n u m b e r o f t r a n s fe r s w h e n
DMAPLUS = 1, since the speed of the accesses will af-
fect the state of the FIFO. During accesses, the FIFO
may be filling or emptying on the network end. A slower
memory response will allow additional data to accumu-
late inside of the FIFO (during write transfers from the
receive FIFO). If the accesses are slow enough, a com-