AM79C961AVIW AMD (ADVANCED MICRO DEVICES), AM79C961AVIW Datasheet - Page 114

• Manufacturer Part Number: AM79C961AVIW
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C961AVIW

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / Rohs Status: Not Compliant

ISA Bus Configuration Registers
The ISA Bus Data Port (IDP) allows access to registers
which are associated with the ISA bus. These registers
are called ISA Bus Configuration Registers (ISACSRs),
and are indexed by the value in the Register Address
Port (RAP). The table below defines the ISACSRs
which can be accessed. All registers are 16 bits. The
“Default” value is the value in the register after reset
and is hexadecimal.Refer to the section “LEDs” for in-
formation on LED control logic.
ISACSR0: Master Mode Read Active/SRAM Data
Port
When in the Bus Master mode:
Bit
15-4
3-0
114
This value can be 0000H for systems that do not support
EEPROM option.
ISACSR
0
1
2
3
4
5
6
7
8
9
MSRDA
Name
RES
MNEMONIC
MSWRA
MSRDA
LED0
LED1
LED2
LED3
DUP
MC
EC
SC
Reserved locations. Written as
zero and read as undefined.
Master Mode Read Active time.
This register is used to tune the
MEMR command signal active
time when the PCnet-ISA II is in
the Bus Master mode. The value
stored in MSRDA defines the
number of 50 ns periods that the
command signal is active. The
default value of 5h indicates
250ns pulse widths. A value of 0
should not be used and may
result in no command assertion.
Default
8000H*
0005H
0005H
0002H
0000H
0084H
0008H
0090H
0000H
0000H
Description
Master Mode
Read Active
Master Mode
Write Active
Miscellaneous
Configuration
EEPROM
Configuration
Link Integrity
Default: RCV
Default:
RCVPOL
Default: XMT
Software
Configuration
(Read-Only
register)
Default: Half
Duplex
Name
Am79C961A
When in the Bus Slave, Programmed I/O architecture
mode:
15-0 SRAMDP
ISACSR1: Master Mode Write Active/SRAM
Address Pointer
When in the Bus Master mode:
Bit
15-4
3-0
When in the Bus Slave, Programmed I/O architecture
mode:
15-0 SRAMAP
MSWRA
Name
RES
SRAM Data Port. This register
serves as a data port for access-
ing the SRAM when the PC-
net-ISA II is in the Bus Slave,
Programmed
mode. Accesses to this port are
directed to the SRAM location
that
SRAMAP register (ISACSR1).
Word
accesses to the even byte (least
significant bits) are allowed. Byte
accesses to the odd byte are not
allowed except when they are
performed
motherboard logic as discussed
in the Bus Cycles (Hardware)
section.
accesses to this register will have
the side effect that the SRAMAP
register (ISACSR1) will incre-
ment by 1 or 2 depending on
whether a byte or word access,
respectively, is performed.
Reserved locations. Written as
zero and read as undefined.
Master Mode Write Active time.
This register is used to tune the
MEMW command signal active
time when the PCnet-ISA II is in
the Bus Master mode. The value
stored in MSWRA defines the
number of 50 ns periods that the
command signal is active. The
default value of 5h indicates
250ns pulse widths. A value of 0
should not be used and may
result in no command assertion.
SRAM Address Pointer. This
register functions as an address
pointer for accessing the SRAM
when the PCnet-ISA II is in the
Bus Slave, Programmed I/O
architecture mode. Accesses to
the SRAMDP (ISACSR0) regis-
ter are directed to the SRAM
location that is addressed by this
register. This register is auto-
is
accesses
Description
addressed
Read
automatically
I/O
and
architecture
and
by
write
byte
the
by