IXB28504XGBEFS Intel, IXB28504XGBEFS Datasheet - Page 121

• Manufacturer Part Number: IXB28504XGBEFS
• Manufacturer: Intel

Specifications of IXB28504XGBEFS

• Lead Free Status / Rohs Status: Compliant

Network Processor Firmware—IXB2850
9.6.1.1
Note:
9.6.2
9.6.3
January 2007
Document Number: 05-2443-006
Reset Interrupt
IXB2850 boards support the “Soft Reset” startup procedure. The XScale core as well as
SRAM and DRAM memory controller are not reset during this kind of boot procedure. To
make the Soft Reset possible, the CPLD device responsible for the NPU hardware reset
generates the NPU interrupt to allow a software controlled NPU reset. The Linux routine
supporting this interrupt should perform the following operation:
Do not enable flash memory aliasing. Typically, the XScale core in the IXP2850 network
processor is mapped to address 0xC400 0000 in the memory map. Flash memory
aliasing is a network processor feature that allows the XScale core to see flash memory
at address 0x0 in the memory map (when DRAM is physically connected). This feature
allows the network processor to boot from flash memory.
IXB2850 Board Reset
IXB2850 board hardware components can be reset by the software through a special
CPLD 32-bit reset register. See the IXP2800 Network Processor Hardware Reference
Manual and the IXP2800 Network Processor Programmer’s Reference Manual for
details.
By setting individual bits in this register, the LSP kernel can reset:
The board reset procedure takes care of switching to bank 0 of the flash memory
during system reset (see
PCI Memory Remapping
The standard PCI memory address space spans 4 GB (32-bit addresses). The XScale
core 4 GB physical address space reserves only 512 MB for the PCI memory window.
Further addressing is possible by using the PCI_ADDR_EXT register. The Boot Monitor
takes care to configure all possible devices in a single 512MB “block”. During
initialization, the Linux kernel reads the content of the PCI_ADDR_EXT register and
calculates the proper offset between the XScale core physical address and the PCI bus
• Onboard SPI-3/4 Bridge chip
• If the Soft Reset flag in the NPU boot parameters stored on flash memory is
• Clear XScale core cache memory
• Start the Initial Loader from flash memory
• Board Management Controller (BMC)
• Media Access Module SPI-3/4 Bridge chip
• Media Access Module Fork FPGA
• On-board 82546 Dual Port Gigabit Ethernet Controller
• On-board Intel
• On-board Marvell* Alaska 1011 Gigabit Ethernet PHY
• On-board CS8900A 10 Mb Ethernet controller
• On-board 16C550 UART controller
• Fabric Interface Card (FIC, IXB28504XGBEFSx boards only)
• Gigabit Ethernet Mezzanine Card in slot DB#2
cleared, disable the reset timer in the CPLD device and perform Soft Reset startup
procedure. The CPLD starts this timer along with NPU interrupt generation. If this
timer is not disabled (for example, the NPU permanently hangs-up), the NPU is
hardware reset after timer expiry.
®
IXF1104 4x1 Gigabit Ethernet MAC
Section 9.6.4, “Banked Flash Memory Support” on page
Intel NetStructure
®
IXB2850 Packet Processing Boards
122).
TPS
121