IXB28504XGBEFS Intel, IXB28504XGBEFS Datasheet - Page 234

• Manufacturer Part Number: IXB28504XGBEFS
• Manufacturer: Intel

Specifications of IXB28504XGBEFS

• Lead Free Status / Rohs Status: Compliant

C.1.13
C.1.14
C.1.15
Intel NetStructure
TPS
234
®
MSF Tests
These tests perform Media Switch Fabric (MSF) registers verification. The tests cases
presented in the following table are executed.
The user can specify how many times the test is performed (the default is 1).
Microengine Tests
The tests check the control, context, and timer registers accessible by microengines. A
microengine is loaded with very simple code that modifies a selected location in DRAM
(for example, multiplication by 2). The selected memory location is initiated before the
microengine executes the loaded code and verified after execution. The tests cases
presented in the following table are executed.
The user can specify:
Microengines will be completely tested during media tests (see
packet transmission and reception is checked.
Media Access Tests
The test performs MAC/Framer, PHY/Serdes and MIC verification. The test cases
presented in the following table are performed for:
Test ID
00h
01h
Test ID
00h
01h
02h
03h
04h
Test ID
00h
01h
02h
03h
04h
05h
• The microengine number
• How many times test is performed (the default is 1)
• MMC#1devices; not applicable to IXB2850 boards
• MMC#2 devices
• Baseboard devices
• FIC devices
IXB2850 Packet Processing Boards
Description
Registers default values test
Registers write/read test
Description
Control Store test
Register test
MSF CSR test
Timers and Counters test
Context test
Description
Registers default values test for MAC/Framer device
Registers write/read test for MAC/Framer device
Registers default values test for PHY/Serdes device
Registers write/read test for PHY/Serdes device
Registers default values test for MAC/Framer ports
Registers write/read test for MAC/Framer ports
Document Number: 05-2443-006
Section
IXB2850—Diagnostics
C.1.15), where
January 2007