IXB28504XGBEFS Intel, IXB28504XGBEFS Datasheet - Page 77

• Manufacturer Part Number: IXB28504XGBEFS
• Manufacturer: Intel

Specifications of IXB28504XGBEFS

• Lead Free Status / Rohs Status: Compliant

Installation and Configuration—IXB2850
Note:
January 2007
Document Number: 05-2443-006
If you are installing a shelf manager in your AdvancedTCA chassis, J2 pins 1-2 must be
set ON. If you are not installing a shelf manager, J2 pins 1-2 must be set OFF.
• J38: Default settings are:
• J7: Default settings are:
• S1: Default settings are:
• SW1: Determines which UART is active for the serial console port on the front
• J8: General purpose connector for connection to Lattice JTAG programmer, Corelis*
• J9: Lattice JTAG connector (for programming of JTAG router)
• J2: Default settings are:
panel. See
or Multi-ICE* for the Board Management Controller (BMC) and Macraigor* for the
Network Processor (NP).
— 1: ON
— 2: ON
— 3: ON
— 4: OFF
— 5: OFF
— 6: ON
— 7: ON
— 8: OFF
— 1: ON
— 2: ON
— 3: ON
— 4: ON
— 5: ON
— 6: ON
— 7: ON
— 8: OFF
— 1 to 8: ON
— 1: OFF
— 2: ON
— 3: ON
— 4: ON
— Pins 1,2: ON
— Pins 7,8: ON
— Pins 15,17: ON
— All others: OFF
Section 5.1.1, “COM Port” on page 60
Intel NetStructure
for details. Default settings are:
®
IXB2850 Packet Processing Boards
TPS
77