EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 134
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EP1AGX20CF484C6N
Manufacturer Part Number
EP1AGX20CF484C6N
Description
IC ARRIA GX FPGA 20K 484FBGA
Manufacturer
Altera
Series
Arria GXr
Datasheet
1.EP1AGX20CF484C6N.pdf
(234 pages)
Specifications of EP1AGX20CF484C6N
Number Of Logic Elements/cells
21580
Number Of Labs/clbs
1079
Total Ram Bits
1229184
Number Of I /o
230
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Arria™ GX
Number Of Logic Blocks/elements
21580
# I/os (max)
230
Process Technology
CMOS
Operating Supply Voltage (typ)
1.2V
Logic Cells
21580
Ram Bits
1229184
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
No. Of Macrocells
21580
Family Type
Arria GX
No. Of I/o's
230
Operating Frequency Max
622.08MHz
Operating Temperature Range
0°C To +85°C
Logic Case Style
BGA
No. Of Pins
484
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2395
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1AGX20CF484C6N
Manufacturer:
ALTERA
Quantity:
672
4–12
Table 4–8. PCS Latency
Table 4–9. PCS Latency (Part 1 of 2) (Part 1 of 2)
Arria GX Device Handbook, Volume 1
XAUI
PIPE
GIGE
Serial RapidIO
SDI
BASIC Single
Width
Notes to
(1) The latency numbers are with respect to the PLD-transceiver interface clock cycles.
(2) The total latency number is rounded off in the Sum column.
XAUI
PIPE
GIGE
Serial
RapidIO
SDI
Functional Mode
Table
4–8:
×1, ×4
8-bit channel width
×1, ×4
16-bit channel width
1.25 Gbps, 2.5 Gbps,
3.125 Gbps
HD 10-bit channel width
HD, 3G 20-bit channel
width
×1, ×4, ×8
8-bit channel width
×1, ×4, ×8
16-bit channel width
1.25 Gbps, 2.5 Gbps,
3.125 Gbps
HD10-bit channel width
HD, 3G 20-bit channel width
8-bit/10-bit channel width
16-bit/20-bit channel width
Table 4–8
respectively.
—
—
(Note 1)
Configuration
—
—
and
Table 4–9
2–2.5
2–2.5
2–2.5
4–5
4–5
2.5
5
2–2.5
list the transmitter and receiver PCS latency for each mode,
—
—
—
—
—
—
TX PIPE
—
—
—
—
—
—
—
1
1
5.5–6.5
5.5–6.5
11–13
11–13
—
—
—
Comp FIFO
TX Phase
2–3
3–4
3–4
2–3
2–3
2–3
2–3
2–3
2–3
0.5
0.5
0.5
0.5
Receiver PCS Latency
1
1
1
Transmitter PCS Latency
Serializer
—
—
—
—
—
—
1
Byte
1
1
1
1
1
1
1
1
1
Chapter 4: DC and Switching Characteristics
1
1
1
1
1
1
1
© December 2009 Altera Corporation
Machine
TX State
0.5
—
—
—
—
—
—
—
—
1
1
1
1
1
1
1
1–2
2–3
2–3
1–2
1–2
1–2
1–2
Encoder
8B/10B
0.5
0.5
0.5
0.5
0.5
Operating Conditions
1
1
1
1
—
—
—
—
—
1
1
Sum
4–5
6–7
6–7
4–5
4–5
4–5
4–5
4–5
4–5
14–17
21–25
13–16
19–23
9–10
6–7
6–7
(2)