EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 154

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

4–32
Typical Design Performance
User I/O Pin Timing
Arria GX Device Handbook, Volume 1
Table 4–47. Default Loading of Different I/O Standards for Arria GX Devices (Part 2 of 2)
The following section describes the typical design performance for the Arria GX
device family.
Table 4–48
buffer t
non-PLL global clock (GCLK) and a PLL driven global clock (GCLK-PLL). For t
and t
to the GCLK/GCLK-PLL values for the device.
EP1AGX20 I/O Timing Parameters
Table 4–48
EP1AGX20 devices for I/O standards which support general purpose I/O pins.
Table 4–48
Arria GX devices.
1.8 V
1.5 V
PCI
PCI-X
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
Differential SSTL-2 Class I
Differential SSTL-2 Class II
Differential SSTL-18 Class I
Differential SSTL-18 Class II
1.5-V differential HSTL Class I
1.5-V differential HSTL Class II
1.8-V differential HSTL Class I
1.8-V differential HSTL Class II
LVDS
CO
SU
using regional clock, add the value from the adder tables listed for each device
, t
through
through
describes the row pin delay adders when using the regional clock in
H
I/O Standard
, and t
CO
Table 4–77
Table 4–51
are reported for the cases when I/O clock is driven by a
show user I/O pin timing for Arria GX devices. I/O
show the maximum I/O timing parameters for
Capacitive Load
10
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Chapter 4: DC and Switching Characteristics
© December 2009 Altera Corporation
Typical Design Performance
Units
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
SU
, t
H
,