EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 218

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

4–96
DCD Measurement Techniques
Figure 4–11. DCD Measurement Technique for Non-DDIO (Single-Data Rate) Outputs
Arria GX Device Handbook, Volume 1
Figure 4–10. Duty Cycle Distortion
DCD expressed in absolution derivation, for example, D1 or D2 in
clock-period independent. DCD can also be expressed as a percentage, and the
percentage number is clock-period dependent. DCD as a percentage is defined as:
DCD is measured at an FPGA output pin driven by registers inside the corresponding
I/O element (IOE) block. When the output is a single data rate signal (non-DDIO),
only one edge of the register input clock (positive or negative) triggers output
transitions
caused by the clock input buffer or different input I/O standard does not transfer to
the output signal.
However, when the output is a double data rate input/output (DDIO) signal, both
edges of the input clock signal (positive and negative) trigger output transitions
(Figure
affect the output DCD.
(T/2 – D1) / T (the low percentage boundary)
(T/2 + D2) / T (the high percentage boundary)
4–12). Therefore, any distortion on the input clock and the input clock buffer
(Figure
4–11). Therefore, any DCD present on the input clock signal or
CLKH = T/2
Falling Edge A
Ideal Falling Edge
Clock Period (T)
D1
D2
Falling Edge B
CLKL = T/2
Chapter 4: DC and Switching Characteristics
© December 2009 Altera Corporation
Figure
Duty Cycle Distortion
4–10, is