EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 227

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

Chapter 4: DC and Switching Characteristics
External Memory Interface Specifications
Table 4–117. Fast PLL Specifications (Part 2 of 2)
External Memory Interface Specifications
© December 2009 Altera Corporation
t
Note to
(1) This is limited by the I/O f
ARESET_RECONFIG
Table
Name
4–117:
Table 4–118
circuitry used for interfacing with external memory devices.
Table 4–118. DLL Frequency Range Specifications
Table 4–119. DQS Jitter Specifications for DLL-Delayed Clock (tDQS_JITTER) ,
Table 4–120. DQS Phase-Shift Error Specifications for DLL-Delayed Clock (t
Notes to
(1) Peak-to-peak period jitter on the phase-shifted DQS clock. For example, jitter on two delay stages under
(2) Delay stages used for requested DQS phase shift are reported in a project’s Compilation Report in the Quartus II
Number of DQS Delay Buffer Stages
Minimum pulse width
on the
when using PLL
reconfiguration. Reset
the PLL after
scandone
MAX
Number of DQS Delay Buffer Stages
commercial conditions is 200 ps peak-to-peak or 100 ps.
software.
.
Description
areset
Table
Frequency Mode
goes high.
through
4–119:
signal
0
1
2
1
2
3
4
1
2
3
4
Table 4–122
Min
500
list Arria GX device specifications for the dedicated
(2)
Typ
—
Commercial (ps)
Frequency Range (MHz)
110
130
160
80
100 to 175
150 to 230
200 to 310
–6 Speed Grade (ps)
Max
—
105
140
35
70
Arria GX Device Handbook, Volume 1
DQS_PSERR
Industrial (ps)
Units
(Note 1)
ns
110
130
180
210
)
4–105