EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 92

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

2–86
Figure 2–72. Arria GX IOE in Bidirectional I/O Configuration
Notes to
(1) All input signals to the IOE can be inverted at the IOE.
(2) The optional PCI clamp is only available on column I/O pins.
Arria GX Device Handbook, Volume 1
Column, Row,
Interconnect
Figure
or Local
2–72:
ioe_clk[7..0]
In normal bidirectional operation, you can use the input register for input data
requiring fast setup times. The input register can have its own clock input and clock
enable separate from the OE and output registers. The output register can be used for
data requiring fast clock-to-output performance. You can use the OE register for fast
clock-to-output enable timing. The OE and output register share the same clock
source and the same clock enable source from the local interconnect in the associated
LAB, dedicated I/O clocks, and the column and row interconnects.
the IOE in bidirectional configuration.
The Arria GX device IOE includes programmable delays that can be activated to
ensure input IOE register-to-logic array register transfers, input pin-to-logic array
register transfers, or output IOE register-to-pin transfers.
clkout
clkin
oe
ce_out
aclr/apreset
ce_in
sclr/spreset
Chip-Wide Reset
Output Register
OE Register
Input Register
D
CLRN/PRN
ENA
ENA
D
ENA
CLRN/PRN
D
CLRN/PRN
(Note 1)
Q
Q
Q
Drive Strength Control
Open-Drain Output
Pin Delay
Output
Input Register Delay
Logic Array Delay
Input Pin to
Input Pin to
OE Register
t
CO
Delay
V
CCIO
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
PCI Clamp (2)
V
CCIO
Bus-Hold
Termination
Circuit
Figure 2–72
On-Chip
Programmable
Pull-Up
Resistor
I/O Structure
shows