EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 208

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

4–86
Table 4–99. Arria GX Performance Notes
IOE Programmable Delay
Table 4–100. Arria GX IOE Programmable Delay on Row Pins
Arria GX Device Handbook, Volume 1
DSP block
Larger Designs
input register
internal cells
Input delay
from pin to
Input delay
from pin to
Parameter
Delay from
register to
output pin
enable pin
Output
output
delay
Applications
I/O output register
Pad to I/O dataout
Paths Affected
Pad to I/O input
parallel FIR filter
18-bit 4-tap FIR
register
to core
to pad
txz/tzx
For IOE programmable delay, refer to
Table 4–100
8-bit 16-tap
18 x 18-bit
18 x 18-bit
36 x 36-bit
36 x 36-bit
multiplier
multiplier
multiplier
multiplier
multiplier
9 x 9-bit
filter
lists IOE programmable delays.
Available
Settings
64
8
2
2
ALUTs
0
0
0
0
0
0
0
Offset
Min
0
0
0
0
Industrial
Resources Used
Memory Blocks
Offset
1.782
2.054
0.332
Max
0.32
Fast Model
TriMatrix
Table 4–100
0
0
0
0
0
0
0
Offset
Min
Commercial
0
0
0
0
through
DSP Blocks
Offset
1.782
2.054
0.332
Chapter 4: DC and Switching Characteristics
0.32
Max
1
2
4
8
8
8
4
© December 2009 Altera Corporation
Table
Offset
–6 Speed Grade
Min
0
0
0
0
4–101.
–6 Speed Grade
IOE Programmable Delay
Performance
Offset
4.124
4.689
0.717
0.693
335.35
335.35
Max
285.0
174.4
285.0
163.0
163.0
Units
ns
ns
ns
ns