EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 4

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

1–2
Table 1–1. Arria GX Device Features (Part 1 of 2)
Arria GX Device Handbook, Volume 1
Package
ALMs
Equivalent
logic
elements
(LEs)
Transceiver
channels
Transceiver
data rate
Source-
synchronous
receive
channels
Feature
484-pin,
780-pin
(Flip chip)
EP1AGX20C
600 Mbps
to 3.125
21,580
8,632
Gbps
31
C
4
■
Table 1–1
packages.
Main device features:
■
■
■
■
■
■
■
■
■
■
484-pin
(Flip chip)
TriMatrix memory consisting of three RAM block sizes to implement true
dual-port memory and first-in first-out (FIFO) buffers with performance up to
380 MHz
Up to 16 global clock networks with up to 32 regional clock networks per
device
High-speed DSP blocks provide dedicated implementation of multipliers,
multiply-accumulate functions, and finite impulse response (FIR) filters
Up to four enhanced phase-locked loops (PLLs) per device provide spread
spectrum, programmable bandwidth, clock switch-over, and advanced
multiplication and phase shifting
Support for numerous single-ended and differential I/O standards
High-speed source-synchronous differential I/O support on up to 47 channels
Support for source-synchronous bus standards, including SPI-4 Phase 2
(POS-PHY Level 4), SFI-4.1, XSBI, UTOPIA IV, NPSI, and CSIX-L1
Support for high-speed external memory including DDR and DDR2 SDRAM,
and SDR SDRAM
Support for multiple intellectual property megafunctions from Altera
MegaCore
Support for remote configuration updates
600 Mbps to 3.125
31
lists Arria GX device features for FineLine BGA (FBGA) with flip chip
C
EP1AGX35C/D
4
13,408
33,520
Gbps
®
780-pin
(Flip chip)
functions and Altera Megafunction Partners Program (AMPP
31
D
8
484-pin
(Flip chip)
600 Mbps to 3.125
31
C
4
EP1AGX50C/D
20,064
50,160
Gbps
780-pin,
1152-pin
(Flip chip)
31, 42
D
8
484-pin
(Flip chip)
Chapter 1: Arria GX Device Family Overview
31
C
4
600 Mbps to 3.125 Gbps
© December 2009 Altera Corporation
EP1AGX60C/D/E
780-pin
(Flip chip)
24,040
60,100
31
D
8
1152-pin
(Flip chip)
12
42
E
®
Features
SM
)
EP1AGX90E
1152-pin
(Flip chip)
600 Mbps
to 3.125
36,088
90,220
Gbps
12
47
E