EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 150

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

4–28
Table 4–44. Output Timing Measurement Methodology for Output Pins
Arria GX Device Handbook, Volume 1
LVTTL
LVCMOS
2.5 V
1.8 V
1.5 V
PCI
PCI-X
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.2-V HSTL with OCT
Differential SSTL-2 Class I
Differential SSTL-2 Class II
Differential SSTL-18 Class I
Differential SSTL-18 Class II
1.5-V differential HSTL Class I
1.5-V differential HSTL Class II
1.8-V differential HSTL Class I
(5)
(4)
(4)
(4)
(5)
(4)
(4)
I/O Standard
Figure 4–7. Output Delay Timing Reporting Setup Modeled by Quartus II
Notes to
(1) Output pin timing is reported at the output pin of the FPGA device. Additional delays for loading and board trace delay
(2) V
(3) V
need to be accounted for with IBIS model simulations.
CCPD
CCINT
Figure
is 3.085 V unless otherwise specified.
is 1.12 V unless otherwise specified.
4–7:
R
Output
Buffer
V
S
—
—
—
—
—
—
—
25
25
25
25
—
—
—
—
—
25
25
50
25
—
—
—
GND
CCIO
(

)
Output
R
D
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
V
(

MEAS
)
Loading and Termination
R
T
—
—
—
—
—
—
—
50
25
50
25
50
25
50
25
—
50
25
50
25
50
25
50
R
(
S

)
V
GND
TT
(Note
R
C
3.135
3.135
2.375
1.710
1.425
2.970
2.970
2.325
2.325
1.660
1.660
1.660
1.660
1.375
1.375
1.140
2.325
2.325
1.660
1.660
1.375
1.375
1.660
V
T
L
(V)
CCIO
1), (2),
V
Chapter 4: DC and Switching Characteristics
1.123
1.123
0.790
0.790
0.790
0.790
0.648
0.648
1.123
1.123
0.790
0.790
0.648
0.648
0.790
TT
—
—
—
—
—
—
—
—
(3)
(V)
© December 2009 Altera Corporation
Output
Output
C
L
10
10
(pF)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
p
n
R
D
Measurement
V
I/O Timing Model
0.6875
MEAS
1.5675
1.5675
1.1875
0.7125
1.1625
1.1625
0.6875
0.6875
1.1625
1.1625
0.6875
0.855
1.485
1.485
0.570
Point
0.83
0.83
0.83
0.83
0.83
0.83
0.83
(V)