EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 22

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

2–16
Arria GX Device Handbook, Volume 1
Bit-Slip Mode
The word aligner can operate in either pattern detection mode or in bit-slip mode.
The bit-slip mode provides the option to manually shift the word boundary through
the FPGA. This feature is useful for:
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The word aligner outputs a word boundary as it is received from the analog receiver
after reset. You can examine the word and search its boundary in the FPGA. To do so,
assert the rx_bitslip signal. The rx_bitslip signal should be toggled and held
constant for at least two FPGA clock cycles.
For every rising edge of the rx_bitslip signal, the current word boundary is
slipped by one bit. Every time a bit is slipped, the bit received earliest is lost. If bit
slipping shifts a complete round of bus width, the word boundary is back to the
original boundary.
The rx_syncstatus signal is not available in bit-slipping mode.
Channel Aligner
The channel aligner is available only in XAUI mode and aligns the signals of all four
channels within a transceiver. The channel aligner follows the IEEE 802.3ae, clause 48
specification for channel bonding.
The channel aligner is a 16-word FIFO buffer with a state machine controlling the
channel bonding process. The state machine looks for an /A/ (/K28.3/) in each
channel and aligns all the /A/ code groups in the transceiver. When four columns of
/A/ (denoted by //A//) are detected, the rx_channelaligned signal goes high,
signifying that all the channels in the transceiver have been aligned. The reception of
four consecutive misaligned /A/ code groups restarts the channel alignment
sequence and sends the rx_channelaligned signal low.
Longer synchronization patterns than the pattern detector can accommodate
Scrambled data stream
Input stream consisting of over-sampled data
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
Transceivers