EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 228
![IC ARRIA GX FPGA 20K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1AGX20CF484C6N
Manufacturer Part Number
EP1AGX20CF484C6N
Description
IC ARRIA GX FPGA 20K 484FBGA
Manufacturer
Altera
Series
Arria GXr
Datasheet
1.EP1AGX20CF484C6N.pdf
(234 pages)
Specifications of EP1AGX20CF484C6N
Number Of Logic Elements/cells
21580
Number Of Labs/clbs
1079
Total Ram Bits
1229184
Number Of I /o
230
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Arria™ GX
Number Of Logic Blocks/elements
21580
# I/os (max)
230
Process Technology
CMOS
Operating Supply Voltage (typ)
1.2V
Logic Cells
21580
Ram Bits
1229184
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
No. Of Macrocells
21580
Family Type
Arria GX
No. Of I/o's
230
Operating Frequency Max
622.08MHz
Operating Temperature Range
0°C To +85°C
Logic Case Style
BGA
No. Of Pins
484
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2395
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1AGX20CF484C6N
Manufacturer:
ALTERA
Quantity:
672
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4–106
JTAG Timing Specifications
Figure 4–13. Arria GX JTAG Waveforms.
Arria GX Device Handbook, Volume 1
Captured
Table 4–121. DQS Bus Clock Skew Adder Specifications (t
Table 4–122. DQS Phase Offset Delay Per Stage (ps)
Figure 4–13
Notes to
(1) The delay settings are linear.
(2) The valid settings for phase offset are –32 to +31.
(3) The typical value equals the average of the minimum and maximum values.
Driven
Signal
Signal
to be
to be
TMS
TDO
TCK
TDI
Speed Grade
–6
Table
18 DQ per DQS
36 DQ per DQS
4 DQ per DQS
9 DQ per DQS
shows the timing requirements for the JTAG signals
t
Mode
4–122:
JCH
t
t
JPZX
JSZX
t
JCP
t
JSSU
t
JCL
Min
10
t
JSH
Positive Offset
t
t
JPCO
JSCO
t
JPSU
DQS Clock Skew Adder (ps)
Max
16
t
t
JSXZ
JPH
Note (1), (2), (3)
DQS_CLOCK_SKEW_A DDER
40
70
75
95
Chapter 4: DC and Switching Characteristics
t
JPXZ
© December 2009 Altera Corporation
Min
8
Negative Offset
JTAG Timing Specifications
)
Max
12
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