EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 137

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 5: Clock Networks and PLLs in Arria II Devices
PLLs in Arria II Devices
December 2010 Altera Corporation
Post-Scale Counter Cascading
1
The VCO frequency reported by the Quartus II software is the value after the
post-scale counter divider (K).
Each PLL has one pre-scale counter (N) and one multiply counter (M) with a range of
1 to 512 for both M and N. The n counter does not use duty-cycle control because the
only purpose of this counter is to calculate frequency division. There are seven generic
post-scale counters in each PLL that can feed GCLKs, RCLKs, or external clock
outputs. These post-scale counters range from 1 to 512 with a 50% duty cycle setting.
The high- and low-count values for each counter ranges from 1 to 256. The sum of the
high- and low-count values chosen for a design selects the divide value for a given
counter.
The Quartus II software automatically chooses the appropriate scaling factors
according to the input frequency, multiplication, and division values entered into the
ALTPLL megafunction.
Arria II PLLs support post-scale counter cascading to create counters larger than 512.
This is automatically implemented in the Quartus II software by feeding the output of
one C counter into the input of the next C counter, as shown in
Figure 5–28. Counter Cascading for Arria II Devices
Note to
(1) n = 6 for Arria II GX devices. n = 6 or 9 for Arria II GZ devices.
When cascading post-scale counters to implement a larger division of the
high-frequency VCO clock, the cascaded counters behave as one counter with the
product of the individual counter settings. For example, if C0 = 40 and C1 = 20, the
cascaded value is C0 × C1 = 800.
Post-scale counter cascading is set in the configuration file. You cannot accomplish
post-scale counter cascading with PLL reconfiguration.
Figure
5–28:
VCO Output
VCO Output
VCO Output
VCO Output
VCO Output
VCO Output
Arria II Device Handbook Volume 1: Device Interfaces and Integration
C0
C1
C2
C3
C4
Cn
(1)
from preceding
post-scale counter
Figure
5–28.
5–33