EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 188
EP2AGX45DF29I5N
Manufacturer Part Number
EP2AGX45DF29I5N
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX45DF29I5N.pdf
(306 pages)
Specifications of EP2AGX45DF29I5N
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
45125
# I/os (max)
364
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
45125
Ram Bits
3565158.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2AGX45DF29I5N
Manufacturer:
ALTERA
Quantity:
201
Company:
Part Number:
EP2AGX45DF29I5N
Manufacturer:
ALTERA
Quantity:
853
- EP2AGX45CU17C6N PDF datasheet
- EP2AGX45CU17C6N PDF datasheet #2
- EP2AGX45CU17C6N PDF datasheet #3
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- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX45DF29I5N PDF datasheet #6
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6–30
Figure 6–13. Differential SSTL I/O Standard Termination for Arria II Devices
Arria II Device Handbook Volume 1: Device Interfaces and Integration
R
Arria II GX
Devices
R
R
Arria II GZ
Devices
Termination
External
On-Board
Termination
S
S
T
OCT and
OCT for
OCT for
Differential I/O Standards Termination
Differential SSTL Class I
Differential SSTL Class I
Series OCT
Series OCT
1
Transmitter
Transmitter
Transmitter
50 Ω
50 Ω
Arria II devices support differential SSTL-2 and SSTL-18, differential HSTL-18,
HSTL-15, HSTL-12, LVDS, LVPECL, RSDS, and mini-LVDS.
Figure 6–14
devices.
Differential HSTL and SSTL outputs are not true differential outputs. They use two
single-ended outputs with the second output programmed as inverted.
Figure 6–13
Arria II devices.
Differential SSTL Class I
25 Ω
25 Ω
Z
Z
Z
Z
50 Ω
50 Ω
0
0
0
0
= 50
= 50 Ω
= 50
= 50 Ω
50 Ω
show the details of various differential I/O terminations on Arria II
shows the details of differential SSTL I/O standard termination on
V TT V TT
V TT
V TT
V CCIO
50 Ω
50 Ω
50 Ω
100
100
GND
100
100
V CCIO
Receiver
Receiver
Receiver
GND
Parallel OCT
100
Differential SSTL Class II
Series OCT
Series OCT
Differential SSTL Class II
Transmitter
Transmitter
Transmitter
25 Ω
25 Ω
50 Ω
25 Ω
25 Ω
V TT V TT
V TT
V TT
Differential SSTL Class II
V TT
V TT
50 Ω
50 Ω
Z
Z
0
0
50 Ω
= 50 Ω
= 50 Ω
50
50
Chapter 6: I/O Features in Arria II Devices
Z
Z
0
0
50 Ω
50 Ω
= 50
= 50
Termination Schemes for I/O Standards
50 Ω
V TT
V TT
December 2010 Altera Corporation
V TT V TT
Figure 6–13
50 Ω
50 Ω
V CCIO
50 Ω
GND
100
100
100
100
V CCIO
Receiver
Receiver
Receiver
through
GND
Parallel OCT
100
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