EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 439
EP2AGX45DF29I5N
Manufacturer Part Number
EP2AGX45DF29I5N
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX45DF29I5N.pdf
(306 pages)
Specifications of EP2AGX45DF29I5N
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
45125
# I/os (max)
364
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
45125
Ram Bits
3565158.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Part Number:
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Manufacturer:
ALTERA
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Part Number:
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Manufacturer:
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Chapter 1: Transceiver Architecture in Arria II Devices
Functional Modes
Figure 1–52. Transceiver Configurations in Basic Mode with a 10-Bit Wide PMA-to-PCS Interface
Notes to
(1) The 8-bit configuration is listed in
(2) The maximum data rate specification shown in
(3) When you enable byte SERDES, the maximum data is 3G; otherwise, it is 1.92G.
December 2010 Altera Corporation
specifications for other speed grades offered, refer to the
Figure
FPGA Fabric-to-Transceiver
Interface Width
Functional Mode
Data Rate (2)
Number of Channels
Low-Latency PCS
Word Aligner (Pattern Length)
8B/10B Encoder/Decoder
Rate Match FIFO
Byte SERDES (3)
Byte Ordering
FPGA Fabric-to-Transceiver
Interface Frequency (MHz) (2)
TX PCS Latency (FPGA
Fabric-Transceiver Interface
Clock Cycles)
RX PCS Latency (FPGA
Fabric-Transceiver Interface
Clock Cycles)
1–52:
Figure 1–52
functional mode with a 10-bit wide PMA-to-PCS interface.
Disabled
Disabled Enabled
10-Bit
4 - 5.5
9 - 11
240
60-
Disabled
Disabled
Manual Alignment
Disabled
20-Bit
187.5
4 - 5.5
Figure
(7-Bit, 10-Bit)
6 - 8
30-
Disabled Enabled
Disabled
shows Arria II GX and GZ transceiver configurations allowed in Basic
4 - 5.5
9 - 11
8-Bit
1–51.
240
60-
Enabled
Disabled
Disabled
187.5
4 - 5.5
16-Bit
6 - 8
30-
Figure 1–52
Disabled Enabled
Disabled
10-Bit
4 - 5.5
9 - 11
240
60-
Disabled
Disabled
Device Datasheet for Arria II Devices
Disabled
20-Bit
4 - 5.5
is valid only for the -3 speed grade devices with byte SERDES enabled. For data rate
187.5
6 - 8
30-
(7-Bit, 10-Bit)
Bit Slip
Disabled Enabled
Disabled
4 - 5.5 4 - 5.5
9 - 11
8-Bit
240
60-
Disabled
Enabled
Disabled
Disabled
Basic 10-Bit PMA-PCS Interface Width
16-Bit
187.5
6 - 8
30-
Disabled Enabled
Disabled
0.6 - 3.75 Gbps
4 - 5.5 4 - 5.5
10-Bit
9 - 11
×1, ×4, ×8
60-
240
Disabled
Disabled
Disabled
20-Bit
187.5
6 - 8
30-
State Machine (7-Bit, 10-Bit)
Automatic Synchronization
Disabled
Disabled
4 - 5.5
9 - 11
8-Bit
240
60-
Arria II Device Handbook Volume 2: Transceivers
chapter.
Disabled
Disabled
4 - 5.5
16-Bit
187.5
6 - 8
30-
Enabled
Enabled
Enabled
187.5
16-Bit
4 - 5.5
7 - 9
30-
Disabled Enabled
Disabled
20 - 24
4 - 5.5
8-Bit
240
60-
Enabled
Disabled
11.5 -
16-Bit
187.5
4 - 5.5
14.5
30-
(Note 1)
Disabled
Disabled Disabled
10-Bit
3 - 4
3 - 4
240
60-
Enabled
Disabled
Disabled
Disabled
Enabled
20-Bit
3 - 4.5
187.5
3 - 4.5
30-
1–53
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