EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 436

• Manufacturer Part Number: EP2AGX45DF29I5N
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5N

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 45125
• # I/os (max): 364
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 45125
• Ram Bits: 3565158.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–50
PCIe Hard IP Block
Functional Modes
Arria II Device Handbook Volume 2: Transceivers
f
Figure 1–50
PHY MAC, Data Link Layer, and Transaction Layer for PCIe interfaces. When you use
this block, the PIPE interface is used as the interface between the FPGA fabric and the
transceiver.
Figure 1–50. PCIe Hard IP High-Level Block Diagram
This block is enabled only when you use the PCIe MegaCore function. For more
information about using this block, refer to the
You can configure the root port or end point in ×1, ×4, and ×8 modes. You can also
include instances of both the soft and hard IP PCIe MegaCore function in a single
device.
You can configure Arria II GX and GZ transceivers in one of the following functional
modes with the ALTGX MegaWizard Plug-In Manager:
■
■
■
■
■
■
■
■
Basic at 600 Mbps to 6.375 Gbps
Deterministic latency, used for CPRI and OBSAI protocols
GIGE (1.25 Gbps)
PCIe (Gen1 at 2.5 Gbps) (Gen2 at 5.0 Gbps for Arria II GZ devices only)
SDI (HD at 1.485 and 1.4835 Gbps, 3G at 2.97 and 2.967 Gbps)
Serial RapidIO (1.25 Gbps, 2.5 Gbps, and 3.125 Gbps)
SONET/SDH (OC-12 and OC-48) (OC-96 for Arria II GZ devices only)
XAUI (3.125 Gbps up to HiGig and HiGig+ at 3.75 Gbps)
shows the block diagram of the PCIe hard IP block used to implement the
Buffer
Retry
Channel
Virtual
Buffer
RX
Clock & Reset Selection
PCIe Protocal Stack
PCIe hard IP
Chapter 1: Transceiver Architecture in Arria II Devices
PCI Express Compiler User
Interface
December 2010 Altera Corporation
TL
Reconfig
Mnmt IF
Adapter
Local
(LMI)
PCIe
PCIe Hard IP Block
Guide.