EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 258
EP2AGX45DF29I5N
Manufacturer Part Number
EP2AGX45DF29I5N
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX45DF29I5N.pdf
(306 pages)
Specifications of EP2AGX45DF29I5N
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
45125
# I/os (max)
364
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
45125
Ram Bits
3565158.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
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8–18
Figure 8–14. Receiver Datapath in DPA Mode
Notes to
(1) All disabled blocks and signals are grayed out.
(2) In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively.
(3) The rx_out port has a maximum data width of 10 bits.
(4) Arria II GX center/corner PLL or Arria II GZ left/right PLL.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
rx_divfwdclk
rx_outclock
Fabric
FPGA
rx_out
Figure
8–14:
10
DPA Mode
In DPA mode, the DPA circuitry automatically chooses the optimal phase between the
source-synchronous reference clock and the input serial data to compensate for the
skew between the two signals. The reference clock must be a differential signal.
Figure 8–14
serial data into the synchronizer. Use the LVDS_diffioclk clock to read the serial data
from the synchronizer. Use the same LVDS_diffioclk clock in the data realignment
and deserializer blocks.
IOE Supports SDR, DDR, or Non-Registered Datapath
(LOAD_EN, diffioclk)
2
Deserializer
DOUT DIN
shows the DPA mode datapath. Use the DPA_diffioclk clock to write
IOE
2
PLL (4)
(Note
3
DOUT DIN
Multiplier
Bit Slip
Clock
(LVDS_LOAD_EN,
LVDS_diffioclk,
rx_outclk)
1), (2),
diffioclk
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
(3)
rx_inclock
DOUT DIN
Synchronizer
8 Serial LVDS
Clock Phases
LVDS Receiver
3
(DPA_LOAD_EN,
DPA_diffioclk,
rx_divfwdclk)
December 2010 Altera Corporation
Retimed
Data
DPA Clock
DPA Circuitry
DIN
Differential Receiver
+
LVDS Clock Domain
DPA Clock Domain
rx_in
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