AT94S40AL-25DGC Atmel, AT94S40AL-25DGC Datasheet - Page 11

• Manufacturer Part Number: AT94S40AL-25DGC
• Description: IC FPSLIC 40K GATE 25MHZ 256BGA
• Manufacturer: Atmel
• Series: FPSLIC®r

Specifications of AT94S40AL-25DGC

• Core Type: 8-bit AVR
• Speed: 16MHz
• Interface: I²C, UART
• Program Sram Bytes: 20K-32K
• Fpga Sram: 18kb
• Eeprom Size: 1M x 8
• Data Sram Bytes: 4K ~ 16K
• Fpga Core Cells: 2304
• Fpga Gates: 40K
• Fpga Registers: 2862
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 256-CABGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

4.9.5
4.9.5.1
4.9.5.2
2314E–FPSLI–6/05
Reading
Current Address Read
Random Read
Read instructions are initiated similarly to write instructions. However, with the R/W bit in the
Device Address set to one. There are three variants of the read instruction: current address
read, random read and sequential read.
For all reads, it is important to understand that the internal Data Byte address counter maintains
the last address accessed during the previous read or write operation, incremented by one. This
address remains valid between operations as long as the chip power is maintained and the
device remains in 2-wire access mode (i.e., SER_EN is driven Low). If the last operation was a
read at address n, then the current address would be n + 1. If the final operation was a write at
address n, then the current address would again be n + 1 with one exception. If address n was
the last byte address in the page, the incremented address n + 1 would “roll over” to the first byte
address on the next page.
Once the Device Address (with the R/W select bit set to High) is clocked in and acknowledged
by the Configurator, the Data Byte at the current address is serially clocked out by the Configu-
rator in response to the clock from the programmer. The programmer generates a Stop
Condition to accept the single byte of data and terminate the read instruction.
A Random Read is a Current Address Read preceded by an aborted write instruction. The write
instruction is only initiated for the purpose of loading the EEPROM Address Bytes. Once the
Device Address Byte and the EEPROM Address Bytes are clocked in and acknowledged by the
Configurator, the programmer immediately initiates a Current Address Read.
A Random Address Read instruction consists of :
A Current Address Read instruction consists of
a Start Condition
a Device Address with R/W = 0
MS Byte of the EEPROM Address
Next Byte of the EEPROM Address
LS Byte of EEPROM Address
a Start Condition
a Device Address with R/W = 1
a Data Byte from the Configurator
a Stop Condition from the programmer.
a Start Condition
a Device Address with R/W = 1
a Data Byte from the Configurator
a Stop Condition from the programmer.
An Acknowledge Bit from the Configurator
An Acknowledge Bit from the Configurator
An Acknowledge Bit from the Configurator
An Acknowledge bit from the Configurator
An Acknowledge Bit from the Configurator
An Acknowledge Bit from the Configurator
AT94S Secure Family
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