AT94S40AL-25DGC Atmel, AT94S40AL-25DGC Datasheet - Page 16

• Manufacturer Part Number: AT94S40AL-25DGC
• Description: IC FPSLIC 40K GATE 25MHZ 256BGA
• Manufacturer: Atmel
• Series: FPSLIC®r

Specifications of AT94S40AL-25DGC

• Core Type: 8-bit AVR
• Speed: 16MHz
• Interface: I²C, UART
• Program Sram Bytes: 20K-32K
• Fpga Sram: 18kb
• Eeprom Size: 1M x 8
• Data Sram Bytes: 4K ~ 16K
• Fpga Core Cells: 2304
• Fpga Gates: 40K
• Fpga Registers: 2862
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 256-CABGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

4.14
4.14.1
4.14.1.1
4.14.1.2
4.14.1.3
16
Security Bit
AT94S Secure Family
AT17LV512/010 Security Bit Programming
Disabling the Security Bit
Enabling the Security Bit
Verifying the Security Bit
.
4.13
Once the security bit is programmed, data will no longer output from the normal data pad. Once
the fuse is set, any attempt to erase the fuse will cause the configurator to erase all of it
contents.
Write 4 bytes “00 00 00 00” to addresses 800000-800003 two consecutive times, using the pre-
viously defined 2-wire write algorithm. Thereafter, either cycle the power or toggle (HI-LO-HI) the
SER_EN pin in order to disable the security.
Write 4 bytes “FF FF FF FF” to addresses 800000-800003 using the previously defined 2-wire
write algorithm.
Read 4 bytes of data from addresses 800000-800003 using the previously defined 2-wire Ran-
dom Read algorithm. If the data is “FF FF FF FF”, the security bit has been enabled. If the data
is “00 00 00 00”, the security bit has been disabled.
144-pin
LQFP
105
107
53
72
81
Secure FPSLIC Configurator Pin Configurations
CABGA
256-pin
D16
C16
N16
M5
K9
RESET/OE
SER_EN
Name
cSDA
cSCK
CE
I/O
I/O
O
I
I
I
Description
Three-state DATA output for configuration. Open-
collector bi-directional pin for programming.
CLOCK output. Used to increment the internal
address and bit counter for reading and
programming.
RESET/OE input (when SER_EN is High). A Low
level on both the CE and RESET/OE inputs
enables the data output driver. A High level on
RESET/OE resets both the address and bit
counters. The logic polarity of this input is
programmable as either RESET/OE or RESET/OE.
This document describes the pin as RESET/OE.
Chip Enable input. Used for device selection only
when SER_EN is High. A Low level on both CE and
OE enables the data output driver. A High level on
CE disables both the address and bit counters and
forces the device into a low-power mode. Note this
pin will not enable/disable the device in the 2-wire
Serial mode (i.e., when SER_EN is driven Low).
Serial enable is normally High during FPGA
loading operations. Bringing SER_EN Low enables
the programming mode.
2314E–FPSLI–6/05