AT94S40AL-25DGC Atmel, AT94S40AL-25DGC Datasheet - Page 5

• Manufacturer Part Number: AT94S40AL-25DGC
• Description: IC FPSLIC 40K GATE 25MHZ 256BGA
• Manufacturer: Atmel
• Series: FPSLIC®r

Specifications of AT94S40AL-25DGC

• Core Type: 8-bit AVR
• Speed: 16MHz
• Interface: I²C, UART
• Program Sram Bytes: 20K-32K
• Fpga Sram: 18kb
• Eeprom Size: 1M x 8
• Data Sram Bytes: 4K ~ 16K
• Fpga Core Cells: 2304
• Fpga Gates: 40K
• Fpga Registers: 2862
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 256-CABGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

4.3
4.4
2314E–FPSLI–6/05
Bit Format
Start and Stop Conditions
may only drive the cSDA line Low. The system must provide a small pull-up current (1 k equiv-
alent) for the cSDA line.
The MESSAGE FORMAT for read and write instructions consists of the bytes shown in
mat” on page
While writing, the programmer is responsible for issuing the instruction and data. While reading,
the programmer issues the instruction and acknowledges the data from the Configurator as
necessary.
Again, the Acknowledge Bit is asserted on the cSDA line by the receiving device on a byte-by-
byte basis.
The factory blanks devices to all zeros before shipping. The array cannot otherwise be “initial-
ized” except by explicitly writing a known value to each location using the serial protocol
described herein.
Data on the cSDA pin may change only during the cSCK Low time; whereas Start and Stop Con-
ditions are identified as transitions during the cSCK High time.
Write Instruction Message Format
Current Address Read (Extended to Sequential Read) Instruction Message Format
The Start Condition is indicated by a high-to-low transition of the cSDA line when the cSCK line
is High. Similarly, the Stop Condition is generated by a low-to-high transition of the cSDA line
when the cSCK line is High, as shown in
The Start Condition will return the device to the state where it is waiting for a Device Address (its
normal quiescent mode).
The Stop Condition initiates an internally timed write signal whose maximum duration is t
(refer to AC Characteristics table for actual value). During this time, the Configurator must
remain in programming mode (i.e., SER_EN is driven Low). cSDA and cSCK lines are ignored
until the cycle is completed. Since the write cycle typically completes in less than t
we recommend the use of “polling” as described in later sections. Input levels to all other pins
should be held constant until the write cycle has been completed.
CONDITION
START
CONDITION
START
5.
ADDRESS
DEVICE
ADDRESS
DEVICE
(CONFIGURATOR)
ADDRESS BYTE
ACK BIT
MS EEPROM
BYTE 1
DATA
(NEXT) EEPROM
ADDRESS BYTE
(PROGRAMMER)
(CONFIGURATOR)
Figure
ACK BIT
ACK BIT
4-1.
ADDRESS BYTE
LS EEPROM
AT94S Secure Family
BYTE n
DATA
BYTE 1
DATA
CONDITION
BYTE n
DATA
STOP
CONDITION
STOP
WR
seconds,
“Bit For-
WR
5